David Tomaschik has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/33639
Change subject: Add support for MX25U25635F. ......................................................................
Add support for MX25U25635F.
This is a 256Kb part with support for JEDEC 4 byte addressing modes. Tested successfully for probe/read.
Change-Id: I5bdcd32acd1942edf65e50bce0f81c836095ee8c Signed-off-by: David Tomaschik davidtomaschik@google.com --- M flashchips.c 1 file changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/33639/1
diff --git a/flashchips.c b/flashchips.c index d85ea74..09cf8d1 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8868,6 +8868,46 @@
{ .vendor = "Macronix", + .name = "MX25U25635F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25U25635F, + .total_size = 32768, + .page_size = 256, + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_4BA, + .tested = TEST_OK_PR, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + /* TODO: security register */ + .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1650, 2000}, + }, + + { + .vendor = "Macronix", .name = "MX25U51245G", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID,
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/33639 )
Change subject: Add support for MX25U25635F. ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/33639/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33639/1//COMMIT_MSG@10 PS1, Line 10: Tested successfully for probe/read. Any tests with write/erase?
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/33639 )
Change subject: Add support for MX25U25635F. ......................................................................
Patch Set 1: Code-Review+1
(2 comments)
Thanks for your patch. There's one nit in the commit message and some missed erase block commands to be added. Then it's ready to go.
https://review.coreboot.org/#/c/33639/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33639/1//COMMIT_MSG@7 PS1, Line 7: Add support for MX25U25635F. No full-stop at end of summary, please.
https://review.coreboot.org/#/c/33639/1/flashchips.c File flashchips.c:
https://review.coreboot.org/#/c/33639/1/flashchips.c@8884 PS1, Line 8884: { : .eraseblocks = { {4 * 1024, 8192} }, : .block_erase = spi_block_erase_20, : }, { : .eraseblocks = { {32 * 1024, 1024} }, : .block_erase = spi_block_erase_52, : }, { : .eraseblocks = { {64 * 1024, 512} }, : .block_erase = spi_block_erase_d8, : }, { Native 4BA erase versions should also be mentioned: 21, 5c, dc
Hello Angel Pons, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/33639
to look at the new patch set (#2).
Change subject: Add support for MX25U25635F ......................................................................
Add support for MX25U25635F
This is a 256Kb part with support for JEDEC 4 byte addressing modes. Tested successfully for probe/read.
Change-Id: I5bdcd32acd1942edf65e50bce0f81c836095ee8c Signed-off-by: David Tomaschik davidtomaschik@google.com --- M flashchips.c 1 file changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/33639/2
David Tomaschik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/33639 )
Change subject: Add support for MX25U25635F ......................................................................
Patch Set 2:
Patch Set 1: Code-Review+1
(2 comments)
Thanks for your patch. There's one nit in the commit message and some missed erase block commands to be added. Then it's ready to go.
I believe I've addressed the comments you had, but please let me know if I've not done it correctly. This is my first time contributing to this project, but I think I've covered it.
David Tomaschik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/33639 )
Change subject: Add support for MX25U25635F ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/#/c/33639/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/33639/1//COMMIT_MSG@7 PS1, Line 7: Add support for MX25U25635F.
No full-stop at end of summary, please.
Done
https://review.coreboot.org/#/c/33639/1//COMMIT_MSG@10 PS1, Line 10: Tested successfully for probe/read.
Any tests with write/erase?
Unfortunately not, I only have one chip, and it's in a device we can't have down for a significant period of time if things go wrong.
https://review.coreboot.org/#/c/33639/1/flashchips.c File flashchips.c:
https://review.coreboot.org/#/c/33639/1/flashchips.c@8884 PS1, Line 8884: { : .eraseblocks = { {4 * 1024, 8192} }, : .block_erase = spi_block_erase_20, : }, { : .eraseblocks = { {32 * 1024, 1024} }, : .block_erase = spi_block_erase_52, : }, { : .eraseblocks = { {64 * 1024, 512} }, : .block_erase = spi_block_erase_d8, : }, {
Native 4BA erase versions should also be mentioned: 21, 5c, dc
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/33639 )
Change subject: Add support for MX25U25635F ......................................................................
Patch Set 2:
(3 comments)
Thanks for your patch. There's one nit in the commit message and some missed erase block commands to be added. Then it's ready to go.
I believe I've addressed the comments you had, but please let me know if I've not done it correctly.
Some white-space issues and something I forgot to mention ._.
This is my first time contributing to this project, but I think I've covered it.
You are doing great so far :)
https://review.coreboot.org/#/c/33639/1/flashchips.c File flashchips.c:
https://review.coreboot.org/#/c/33639/1/flashchips.c@8884 PS1, Line 8884: { : .eraseblocks = { {4 * 1024, 8192} }, : .block_erase = spi_block_erase_20, : }, { : .eraseblocks = { {32 * 1024, 1024} }, : .block_erase = spi_block_erase_52, : }, { : .eraseblocks = { {64 * 1024, 512} }, : .block_erase = spi_block_erase_d8, : }, {
Done
Sorry, I forgot to mention that order matters, the native 4BA versions should come first. See next chip, for instance.
https://review.coreboot.org/#/c/33639/2/flashchips.c File flashchips.c:
https://review.coreboot.org/#/c/33639/2/flashchips.c@8888 PS2, Line 8888: .eraseblocks = { {4 * 1024, 8192} }, : .block_erase = spi_block_erase_21, : }, { Use tabs for indentation (and one tab is 8 spaces anyway).
https://review.coreboot.org/#/c/33639/2/flashchips.c@8893 PS2, Line 8893: }, { dito
Hello Angel Pons, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/flashrom/+/33639
to look at the new patch set (#3).
Change subject: Add support for MX25U25635F ......................................................................
Add support for MX25U25635F
This is a 256Kb part with support for JEDEC 4 byte addressing modes. Tested successfully for probe/read.
Change-Id: I5bdcd32acd1942edf65e50bce0f81c836095ee8c Signed-off-by: David Tomaschik davidtomaschik@google.com --- M flashchips.c 1 file changed, 49 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/39/33639/3
David Tomaschik has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/33639 )
Change subject: Add support for MX25U25635F ......................................................................
Patch Set 3:
(1 comment)
Thanks for the feedback, and sorry for the slow iteration time.
https://review.coreboot.org/#/c/33639/1/flashchips.c File flashchips.c:
https://review.coreboot.org/#/c/33639/1/flashchips.c@8884 PS1, Line 8884: { : .eraseblocks = { {4 * 1024, 8192} }, : .block_erase = spi_block_erase_20, : }, { : .eraseblocks = { {32 * 1024, 1024} }, : .block_erase = spi_block_erase_52, : }, { : .eraseblocks = { {64 * 1024, 512} }, : .block_erase = spi_block_erase_d8, : }, {
Sorry, I forgot to mention that order matters, the native 4BA versions […]
Done
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/33639 )
Change subject: Add support for MX25U25635F ......................................................................
Patch Set 3: Code-Review+2
Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/flashrom/+/33639 )
Change subject: Add support for MX25U25635F ......................................................................
Add support for MX25U25635F
This is a 256Kb part with support for JEDEC 4 byte addressing modes. Tested successfully for probe/read.
Change-Id: I5bdcd32acd1942edf65e50bce0f81c836095ee8c Signed-off-by: David Tomaschik davidtomaschik@google.com Reviewed-on: https://review.coreboot.org/c/flashrom/+/33639 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M flashchips.c 1 file changed, 49 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/flashchips.c b/flashchips.c index d85ea74..09c4f8e 100644 --- a/flashchips.c +++ b/flashchips.c @@ -8868,6 +8868,55 @@
{ .vendor = "Macronix", + .name = "MX25U25635F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, + .model_id = MACRONIX_MX25U25635F, + .total_size = 32768, + .page_size = 256, + /* OTP: 512B total; enter 0xB1, exit 0xC1 */ + .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_4BA, + .tested = TEST_OK_PR, + .probe = probe_spi_rdid, + .probe_timing = TIMING_ZERO, + .block_erasers = + { + { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_21, + }, { + .eraseblocks = { {4 * 1024, 8192} }, + .block_erase = spi_block_erase_20, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_5c, + }, { + .eraseblocks = { {32 * 1024, 1024} }, + .block_erase = spi_block_erase_52, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_dc, + }, { + .eraseblocks = { {64 * 1024, 512} }, + .block_erase = spi_block_erase_d8, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_60, + }, { + .eraseblocks = { {32 * 1024 * 1024, 1} }, + .block_erase = spi_block_erase_c7, + } + }, + /* TODO: security register */ + .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ + .unlock = spi_disable_blockprotect_bp3_srwd, + .write = spi_chip_write_256, /* Multi I/O supported */ + .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ + .voltage = {1650, 2000}, + }, + + { + .vendor = "Macronix", .name = "MX25U51245G", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID,
-
Angel Pons (Code Review) -
David Tomaschik (Code Review)
-
Nico Huber (Code Review)