Change in flashrom[master]: RFC: flashchips.c: merge GD25B128B/GD25Q128B and GD25Q127C/GD25Q128C
Nikolai Artemiev has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/52883 ) Change subject: RFC: flashchips.c: merge GD25B128B/GD25Q128B and GD25Q127C/GD25Q128C ...................................................................... RFC: flashchips.c: merge GD25B128B/GD25Q128B and GD25Q127C/GD25Q128C Both the 'B' and 'C' chips have the same vendor / device ID, leading to flashrom not being able to automatically identify them. The only difference between the definitions is that the 'C' chips have FEATAURE_QPI and 'B' chips don't. For now this has been resolved by removing that feature bit. Change-Id: I688f2e15aef61afbec728a9a81094bee56d6fbfa Signed-off-by: Nikolai Artemiev <nartemiev@google.com> --- M flashchips.c 1 file changed, 9 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/83/52883/1 diff --git a/flashchips.c b/flashchips.c index 6482f67..81ee9fb 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6271,13 +6271,18 @@ { .vendor = "GigaDevice", - .name = "GD25B128B/GD25Q128B", + .name = "GD25B128B/GD25Q128B/GD25Q127C/GD25Q128C", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, .model_id = GIGADEVICE_GD25Q128, .total_size = 16384, .page_size = 256, - /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ + /* OTP: read 0x48; write 0x42; erase 0x44 + GD25B128B/GD25Q128B: 1024B total, 256B reserved + GD25Q127C/GD25Q128C: 1536B total, 256B reserved + + QPI: GD25B128B/GD25Q128B: QPI support unknown + GD25Q127C/GD25Q128C: enable 0x38, disable 0xFF */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .tested = TEST_OK_PREW, .probe = probe_spi_rdid, @@ -6301,8 +6306,9 @@ .block_erase = spi_block_erase_c7, } }, + /* TODO: 2nd status reg (read 0x35, write 0x31) and 3rd status reg (read 0x15, write 0x11) */ .printlock = spi_prettyprint_status_register_bp4_srwd, - .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .unlock = spi_disable_blockprotect_bp4_srwd, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {2700, 3600}, @@ -6582,47 +6588,6 @@ { .vendor = "GigaDevice", - .name = "GD25Q127C/GD25Q128C", - .bustype = BUS_SPI, - .manufacture_id = GIGADEVICE_ID, - .model_id = GIGADEVICE_GD25Q128, - .total_size = 16384, - .page_size = 256, - /* OTP: 1536B total; read 0x48; write 0x42, erase 0x44 */ - /* QPI: enable 0x38, disable 0xFF */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_OK_PREW, - .probe = probe_spi_rdid, - .probe_timing = TIMING_ZERO, - .block_erasers = - { - { - .eraseblocks = { {4 * 1024, 4096} }, - .block_erase = spi_block_erase_20, - }, { - .eraseblocks = { {32 * 1024, 512} }, - .block_erase = spi_block_erase_52, - }, { - .eraseblocks = { {64 * 1024, 256} }, - .block_erase = spi_block_erase_d8, - }, { - .eraseblocks = { {16 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_60, - }, { - .eraseblocks = { {16 * 1024 * 1024, 1} }, - .block_erase = spi_block_erase_c7, - } - }, - /* TODO: 2nd status reg (read 0x35, write 0x31) and 3rd status reg (read 0x15, write 0x11) */ - .printlock = spi_prettyprint_status_register_bp4_srwd, - .unlock = spi_disable_blockprotect_bp4_srwd, - .write = spi_chip_write_256, - .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ - .voltage = {2700, 3600}, - }, - - { - .vendor = "GigaDevice", .name = "GD25Q16(B)", .bustype = BUS_SPI, .manufacture_id = GIGADEVICE_ID, -- To view, visit https://review.coreboot.org/c/flashrom/+/52883 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I688f2e15aef61afbec728a9a81094bee56d6fbfa Gerrit-Change-Number: 52883 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Artemiev <nartemiev@google.com> Gerrit-MessageType: newchange
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Nikolai Artemiev (Code Review)