Change in flashrom[master]: chipset_enable.c: Mark Intel Q67 as DEP
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/47797 ) Change subject: chipset_enable.c: Mark Intel Q67 as DEP ...................................................................... chipset_enable.c: Mark Intel Q67 as DEP Tested reading, writing and erasing the internal flash chip using an HP Elite 8200 mainboard with an Intel Q67 PCH. However, since ME-enabled chipsets are marked as DEP instead of OK, this one shall also be. Change-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554 Signed-off-by: Angel Pons <th3fanbus@gmail.com> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/flashrom refs/changes/97/47797/1 diff --git a/chipset_enable.c b/chipset_enable.c index 04ff9d8..5e4a547 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1829,7 +1829,7 @@ {0x8086, 0x1c4b, B_FS, NT, "Intel", "HM67", enable_flash_pch6}, {0x8086, 0x1c4c, B_FS, NT, "Intel", "Q65", enable_flash_pch6}, {0x8086, 0x1c4d, B_FS, NT, "Intel", "QS67", enable_flash_pch6}, - {0x8086, 0x1c4e, B_FS, NT, "Intel", "Q67", enable_flash_pch6}, + {0x8086, 0x1c4e, B_FS, DEP, "Intel", "Q67", enable_flash_pch6}, {0x8086, 0x1c4f, B_FS, DEP, "Intel", "QM67", enable_flash_pch6}, {0x8086, 0x1c50, B_FS, NT, "Intel", "B65", enable_flash_pch6}, {0x8086, 0x1c52, B_FS, NT, "Intel", "C202", enable_flash_pch6}, -- To view, visit https://review.coreboot.org/c/flashrom/+/47797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554 Gerrit-Change-Number: 47797 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus@gmail.com> Gerrit-MessageType: newchange
Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47797 ) Change subject: chipset_enable.c: Mark Intel Q67 as DEP ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/flashrom/+/47797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554 Gerrit-Change-Number: 47797 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks@gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Fri, 20 Nov 2020 09:14:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47797 ) Change subject: chipset_enable.c: Mark Intel Q67 as DEP ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/flashrom/+/47797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554 Gerrit-Change-Number: 47797 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks@gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Fri, 20 Nov 2020 09:19:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment
Angel Pons has submitted this change. ( https://review.coreboot.org/c/flashrom/+/47797 ) Change subject: chipset_enable.c: Mark Intel Q67 as DEP ...................................................................... chipset_enable.c: Mark Intel Q67 as DEP Tested reading, writing and erasing the internal flash chip using an HP Elite 8200 mainboard with an Intel Q67 PCH. However, since ME-enabled chipsets are marked as DEP instead of OK, this one shall also be. Change-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> --- M chipset_enable.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, but someone else must approve Edward O'Callaghan: Looks good to me, approved diff --git a/chipset_enable.c b/chipset_enable.c index 04ff9d8..5e4a547 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -1829,7 +1829,7 @@ {0x8086, 0x1c4b, B_FS, NT, "Intel", "HM67", enable_flash_pch6}, {0x8086, 0x1c4c, B_FS, NT, "Intel", "Q65", enable_flash_pch6}, {0x8086, 0x1c4d, B_FS, NT, "Intel", "QS67", enable_flash_pch6}, - {0x8086, 0x1c4e, B_FS, NT, "Intel", "Q67", enable_flash_pch6}, + {0x8086, 0x1c4e, B_FS, DEP, "Intel", "Q67", enable_flash_pch6}, {0x8086, 0x1c4f, B_FS, DEP, "Intel", "QM67", enable_flash_pch6}, {0x8086, 0x1c50, B_FS, NT, "Intel", "B65", enable_flash_pch6}, {0x8086, 0x1c52, B_FS, NT, "Intel", "C202", enable_flash_pch6}, -- To view, visit https://review.coreboot.org/c/flashrom/+/47797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554 Gerrit-Change-Number: 47797 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks@gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-MessageType: merged
xin hua wang has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47797 ) Change subject: chipset_enable.c: Mark Intel Q67 as DEP ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: write is not working for me, log below flashrom v1.2 on Linux 5.13.0-19-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.6.4, GCC 9.2.1 20200304, little endian Command line (10 args): flashrom -V -p internal -c MX25L6406E/MX25L6408E --ifd -i bios -w build/coreboot.rom Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer /sys/class/mtd/mtd0 does not exist No coreboot table found. Using Internal DMI decoder. No DMI table found. W836xx enter config mode worked or we were already in config mode. W836xx leave config mode had no effect. Active config mode, unknown reg 0x20 ID: 1c. Found chipset "Intel Q67" with PCI ID 8086:1c4e. This chipset is marked as untested. If you are using an up-to-date version of flashrom *and* were (not) able to successfully update your firmware with it, then please email a report to flashrom@flashrom.org including a verbose (-V) log. Thank you! Enabling flash write... Root Complex Register Block address = 0xfed1c000 GCS = 0xc05: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x3 (SPI) Top Swap: not enabled 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x0 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x1 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x2 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x3 0x7fffffff/0x7fffffff FWH IDSEL: 0x4 0x7fffffff/0x7fffffff FWH IDSEL: 0x5 0x7fffffff/0x7fffffff FWH IDSEL: 0x6 0x7fffffff/0x7fffffff FWH IDSEL: 0x7 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode enabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled 0x7fffffff/0x7fffffff FWH decode disabled Maximum FWH chip size: 0x100000 bytes SPI Read Configuration: prefetching disabled, caching enabled, BIOS_CNTL = 0x02: BIOS Lock Enable: enabled, BIOS Write Enable: disabled Warning: Setting Bios Control at 0xdc from 0x02 to 0x01 failed. New value is 0x02. SPIBAR = 0x00007fe7156a5000 + 0x3800 0x04: 0xc008 (HSFS) HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=0, FDV=1, FLOCKDN=1 SPI Configuration is locked down. The Flash Descriptor Override Strap-Pin is set. Restrictions implied by the Master Section of the flash descriptor are NOT in effect. Please note that Protected Range (PR) restrictions still apply. Reading OPCODES... done 0x06: 0x0000 (HSFC) HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0 0x50: 0x0000ffff (FRAP) BMWAG 0x00, BMRAG 0x00, BRWA 0xff, BRRA 0xff 0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is read-write. 0x58: 0x07ff0510 FREG1: BIOS region (0x00510000-0x007fffff) is read-write. 0x5C: 0x050f0003 FREG2: Management Engine region (0x00003000-0x0050ffff) is read-write. 0x60: 0x00020001 FREG3: Gigabit Ethernet region (0x00001000-0x00002fff) is read-write. 0x90: 0x84 (SSFS) SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 0x91: 0xf94130 (SSFC) SSFC: SCGO=0, ACS=0, SPOP=0, COP=3, DBC=1, SME=0, SCF=1 0x94: 0x0006 (PREOP) 0x96: 0x043b (OPTYPE) 0x98: 0x05200302 (OPMENU) 0x9c: 0x0000019f (OPMENU+4) 0xa0: 0x00000000 (BBAR) 0xc4: 0x00802005 (LVSCC) LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1 0xc8: 0x00002005 (UVSCC) UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 0xd0: 0x00000000 (FPB) OK. The following protocols are supported: SPI. Probing for Macronix MX25L6406E/MX25L6408E, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 Found Macronix flash chip "MX25L6406E/MX25L6408E" (8192 kB, SPI) mapped at physical address 0x00000000ff800000. Chip status register is 0x00. Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set Chip status register: Bit 6 is not set Chip status register: Block Protect 3 (BP3) is not set Chip status register: Block Protect 2 (BP2) is not set Chip status register: Block Protect 1 (BP1) is not set Chip status register: Block Protect 0 (BP0) is not set Chip status register: Write Enable Latch (WEL) is not set Chip status register: Write In Progress (WIP/BUSY) is not set This chip may contain one-time programmable memory. flashrom cannot read and may never be able to write it, hence it may not be able to completely clone the contents of this chip (see man page for details). Reading ich descriptor... done. Peculiar firmware descriptor, assuming Ibex Peak compatibility. Using region: "bios". coreboot last image size (not ROM size) is 8388608 bytes. Manufacturer: HP Mainboard ID: HP Compaq 8200 Elite SFF PC Reading old flash chip contents... done. Erasing and writing flash chip... Trying erase function 0... 0x510000-0x510fff:ETransaction error! SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 SSFC: SCGO=0, ACS=1, SPOP=0, COP=2, DBC=0, SME=0, SCF=1 Running OPCODE 0x20 failed at address 0x510000 (payload length was 0). spi_write_cmd failed during command execution at address 0x510000 Reading current flash chip contents... done. Looking for another erase function. Trying erase function 1... 0x510000-0x51ffff:EInvalid OPCODE 0x06, will not execute. spi_write_cmd failed during command execution at address 0x510000 Reading current flash chip contents... done. Looking for another erase function. Trying erase function 2... 0x510000-0x51ffff:EInvalid OPCODE 0x06, will not execute. spi_write_cmd failed during command execution at address 0x510000 Reading current flash chip contents... done. Looking for another erase function. Trying erase function 3... 0x000000-0x7fffff:RREInvalid OPCODE 0x06, will not execute. spi_simple_write_cmd failed during command execution Reading current flash chip contents... done. Looking for another erase function. Trying erase function 4... 0x000000-0x7fffff:RREInvalid OPCODE 0x06, will not execute. spi_simple_write_cmd failed during command execution Reading current flash chip contents... done. Looking for another erase function. Trying erase function 5... not defined. Looking for another erase function. Trying erase function 6... not defined. Looking for another erase function. Trying erase function 7... not defined. No usable erase functions left. FAILED! Uh oh. Erase/write failed. Checking if anything has changed. Reading current flash chip contents... done. Good, writing to the flash chip apparently didn't do anything. This means we have to add special support for your board, programmer or flash chip. Please report this on IRC at chat.freenode.net (channel #flashrom) or mail flashrom@flashrom.org, thanks! ------------------------------------------------------------------------------- You may now reboot or simply leave the machine running. Restoring MMIO space at 0x7fe7156a88a0 Restoring PCI config space for 00:1f:0 reg 0xdc -- To view, visit https://review.coreboot.org/c/flashrom/+/47797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554 Gerrit-Change-Number: 47797 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks@gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: xin hua wang <xinhuawang0101@gmail.com> Gerrit-Comment-Date: Sun, 31 Oct 2021 06:26:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/flashrom/+/47797 ) Change subject: chipset_enable.c: Mark Intel Q67 as DEP ...................................................................... Patch Set 2: (1 comment) Patchset: PS2:
Warning: Setting Bios Control at 0xdc from 0x02 to 0x01 failed. New value is 0x02.
This line from your log is saying that SMM BWP (BIOS Write Protection) is enabled. This means the currently-running firmware prevents writes to the flash chip. Unfortunately, it's not a flashrom problem. -- To view, visit https://review.coreboot.org/c/flashrom/+/47797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: flashrom Gerrit-Branch: master Gerrit-Change-Id: I2bd431c5c72824654b6b5b840f9af55dfe9d3554 Gerrit-Change-Number: 47797 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks@gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec@chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks@eltan.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: xin hua wang <xinhuawang0101@gmail.com> Gerrit-Comment-Date: Mon, 01 Nov 2021 10:42:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: xin hua wang <xinhuawang0101@gmail.com> Gerrit-MessageType: comment
participants (4)
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Angel Pons (Code Review) -
Edward O'Callaghan (Code Review)
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Frans Hendriks (Code Review)
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xin hua wang (Code Review)