Subrata Banik has uploaded this change for review.
ichspi: Introduce HSFC FCYCLE(cyc)/FCYCLE_MASK(n) macros
This patch introduces useful HSFC_FCYCLE(cyc) and HSFC_FCYCLE_MASK(n)
macros to cover both ICH and PCH hardware sequencing FCYCLEÂ Bit width.
Also, drops unused macros (PCH100_HSFC_FCYCLE_OFF and
PCH100_HSFC_FCYCLE).
BUG=b:223630977
TEST=Able to perform read/write/erase operation on brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id222304165610c7ae48e365d72ec8fdeea51c51d
---
M ichspi.c
1 file changed, 11 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/91/62891/1
diff --git a/ichspi.c b/ichspi.c
index 9146dac..3f7083c 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -78,8 +78,6 @@
*/
/* Changed HSFC Control bits */
-#define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */
-#define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF)
/* New HSFC Control bit */
#define PCH100_FADDR_FLA 0x07ffffff
@@ -137,8 +135,11 @@
#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
-#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
-#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
+#define HSFC_FCYCLE_BIT_WIDTH_ICH9 3 /* 2 bits */
+#define HSFC_FCYCLE_BIT_WIDTH_PCH 0xf /* 4 bits */
+#define HSFC_FCYCLE_OFF 1 /* 1-HSFC_FCYCLE_BIT_WIDTH_x: FLASH Cycle */
+#define HSFC_FCYCLE_MASK(n) (n << HSFC_FCYCLE_OFF)
+#define HSFC_FCYCLE(cyc) ((cyc) << HSFC_FCYCLE_OFF)
#define HSFC_WET_OFF 5 /* 5: Write Enable Type */
#define HSFC_WET (0x1 << HSFC_WET_OFF)
/* 3-7: reserved */
@@ -495,11 +496,13 @@
case CHIPSET_400_SERIES_COMET_POINT:
case CHIPSET_500_SERIES_TIGER_POINT:
case CHIPSET_ELKHART_LAKE:
- _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
+ _pprint_reg(HSFC, HSFC_FCYCLE_MASK(HSFC_FCYCLE_BIT_WIDTH_PCH), HSFC_FCYCLE_OFF,
+ reg_val, ", ");
pprint_reg(HSFC, WET, reg_val, ", ");
break;
default:
- pprint_reg(HSFC, FCYCLE, reg_val, ", ");
+ _pprint_reg(HSFC, HSFC_FCYCLE_MASK(HSFC_FCYCLE_BIT_WIDTH_ICH9), HSFC_FCYCLE_OFF,
+ reg_val, ", ");
break;
}
pprint_reg(HSFC, FDBC, reg_val, ", ");
@@ -1838,7 +1841,7 @@
swseq->reg_opmenu = PCH100_REG_OPMENU;
hwseq->addr_mask = PCH100_FADDR_FLA;
hwseq->only_4k = true;
- hwseq->hsfc_fcycle = PCH100_HSFC_FCYCLE;
+ hwseq->hsfc_fcycle = HSFC_FCYCLE_MASK(HSFC_FCYCLE_BIT_WIDTH_PCH);
break;
default:
*num_pr = 5;
@@ -1849,7 +1852,7 @@
swseq->reg_opmenu = ICH9_REG_OPMENU;
hwseq->addr_mask = ICH9_FADDR_FLA;
hwseq->only_4k = false;
- hwseq->hsfc_fcycle = HSFC_FCYCLE;
+ hwseq->hsfc_fcycle = HSFC_FCYCLE_MASK(HSFC_FCYCLE_BIT_WIDTH_ICH9);
break;
}
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