View Change

1 comment:

• File bitbang_spi.c:

  • Patch Set #2, Line 157: bitbang_spi_set_sck(master, 0);

    I did spend some time on the page... but I don't recall studying the timing diagram much. […]

    "For the first cycle, ..." that is actually redundant with the
    first sentence behind that bullet. And it must be true for all
    bits. But I agree they try to define an exception somehow for
    the first bit, but fail to specify it correctly.

    What I was nitpicking is that if you define that MOSI is always
    changed on a falling edge, then we don't comply because we don't
    have an edge for the first bit. I guess now, the first sentence
    behind that bullet just doesn't apply to the first bit for the
    available hardware implementations. So there is nothing to argue
    about any more ;) it depends on how you define CPHA=0 and it
    seems nobody defined it.

    CPOL=1 CPHA=1 seems overall less ambiguous too me, maybe that's
    why I would prefer it.

To view, visit change 26946. To unsubscribe, or for help writing mail filters, visit settings.