Attention is currently required from: Nico Huber, Patrick Georgi, Martin Roth, Caveh Jalali, Stefan Reinauer, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Alex Levin, Nick Vaccaro, YH Lin, Boris Mittelberg.
1 comment:
Patchset:
My recommendation was given in my very first comment on this change and was
repeated later. You choose to ignore it from the beginning. I can't help you
there any more.
I've tried to respond to each questions being asked and shared the possible information that we are getting out from debug. Sometime early debug data was misleading (like, I suspected CSE FW is accessing the SPI bus when we are seeing 61849 is failing at Host side) and then have clarified saying (multiple processes might trying to access the same flashrom at host side is the culprit). Please help me know which one you felt is being ignored.
Nobody is walking away here.
It sounds like walking but I'm happy if that's not the case.
It will just take time to answer your questions
Sure, take time, In either case I was not going to merge this CL with just one +2 from Intel (Rizwan) and waited for community for review time.
.(I tried to answer everything that was on topic so far). You can't expect
reviewers to quit their day jobs to attend your changes full-time.
No I don't either, but they do ack when they are actively reviewing a change and help to fix a problem which is paining.
I might be wrong, bt felt that you just drop your -2 without leaving comment on previous discussions (I agree those might be over weekend and that shared the urgency about the failure), especially this one,
Please see this, prior to Intel HW seq, we always used SCIP for syncing between the operations.
https://github.com/flashrom/flashrom/blob/master/ichspi.c#L968
Hence, I told, this is missing step in HW seq (and not only in flashrom but in coreboot CB:61849 and https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/3455264)
I do respect your contribution and help. Kindly keep it in that way going forward to.
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