Anastasia Klimchuk submitted this change.
flashchips: Add Puya P25Q21H/11H/06H
Datasheet:
https://semic-boutique.com/wp-content/uploads/2016/05/P25Q21H-SSH-IT.pdf
Tested P25Q21H read, write and probe with CH341a.
Signed-off-by: Nita Vesa <werecatf@outlook.com>
Change-Id: Idd43145c72607837cb7afa1b007e68eb8e63ebd9
Signed-off-by: Anastasia Klimchuk <aklm@flashrom.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58134
Reviewed-by: Alexander Goncharov <chat@joursoir.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M flashchips.c
M include/flashchips.h
2 files changed, 134 insertions(+), 0 deletions(-)
diff --git a/flashchips.c b/flashchips.c
index 9210de2..d80a574 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -14130,6 +14130,135 @@
},
{
+ .vendor = "PUYA",
+ .name = "P25Q06H",
+ .bustype = BUS_SPI,
+ .manufacture_id = PUYA_ID,
+ .model_id = PUYA_P25Q06H,
+ .total_size = 64,
+ .page_size = 256,
+ /* supports SFDP */
+ /* OTP: 3 x 512 bytes */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .tested = TEST_UNTESTED,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {256, 256} },
+ .block_erase = SPI_BLOCK_ERASE_81,
+ }, {
+ .eraseblocks = { {4 * 1024, 16} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 2} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {64 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {64 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ,
+ .voltage = {2300, 3600},
+ },
+
+ {
+ .vendor = "PUYA",
+ .name = "P25Q11H",
+ .bustype = BUS_SPI,
+ .manufacture_id = PUYA_ID,
+ .model_id = PUYA_P25Q11H,
+ .total_size = 128,
+ .page_size = 256,
+ /* supports SFDP */
+ /* OTP: 3 x 512 bytes */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .tested = TEST_UNTESTED,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {256, 512} },
+ .block_erase = SPI_BLOCK_ERASE_81,
+ }, {
+ .eraseblocks = { {4 * 1024, 32} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 4} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 2} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {128 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {128 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ,
+ .voltage = {2300, 3600},
+ },
+
+ {
+ .vendor = "PUYA",
+ .name = "P25Q21H",
+ .bustype = BUS_SPI,
+ .manufacture_id = PUYA_ID,
+ .model_id = PUYA_P25Q21H,
+ .total_size = 256,
+ .page_size = 256,
+ /* supports SFDP */
+ /* OTP: 3 x 512 bytes */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .tested = TEST_OK_PREW,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {256, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_81,
+ }, {
+ .eraseblocks = { {4 * 1024, 64} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 8} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 4} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {256 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {256 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ,
+ .voltage = {2300, 3600},
+ },
+
+ {
.vendor = "SST",
.name = "SST25LF020A",
.bustype = BUS_SPI,
diff --git a/include/flashchips.h b/include/flashchips.h
index 962e65e..1150ff5 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -635,6 +635,11 @@
#define PMC_PM49FL002 0x6D
#define PMC_PM49FL004 0x6E
+#define PUYA_ID 0x85
+#define PUYA_P25Q06H 0x4010
+#define PUYA_P25Q11H 0x4011
+#define PUYA_P25Q21H 0x4012
+
/*
* The Sanyo chip found so far uses SPI, first byte is manufacturer code,
* second byte is the device code,
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