Anastasia Klimchuk submitted this change.
flashchips: Split and add write-protect support for MX25L12833F
MX25L12833F datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8934/MX25L12833F,%203V,%20128Mb,%20v1.0.pdf
Status register: page 30 table 7 (BP0~BP3, SRWD)
Configuration register: page 31 table 8 (TB)
Security register: page 57 table 12 (WPSEL)
MX25L12835F datasheet:
https://www.macronix.com/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf
Status register: page 31(BP0~BP3, SRWD)
Configuration register: page 32 table 7 (TB)
Security register: page 61 table 9 (WPSEL)
MX25L12845E datasheet: (no CONFIG)
https://www.mxic.com.tw/Lists/Datasheet/Attachments/8693/MX25L12845E,%203V,%20128Mb,%20v1.9.pdf
Status register: page 17 (BP0~BP3, SRWD)
Security register: page 29 (WPSEL)
MX25L12865E datasheet: (no CONFIG)
https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L6465E,_MX25L12865E.pdf
Status register: page 19 (BP0~BP3, SRWD)
Security register: page 31 (WPSEL)
MX25L12873F datasheet: (no hardware WP)
https://www.mxic.com.tw/Lists/Datasheet/Attachments/8652/MX25L12873F,%203V,%20128Mb,%20v1.2.pdf
Status register: page 31(BP0~BP3, SRWD)
Configuration register: page 32 table 7 (TB)
Security register: page 60 table 9 (WPSEL)
Splits the MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F
group into three subgroups:
* MX25L12833F: This chip have the configuration register and WP tested
* MX25L12835F/MX25L12873F: These chips have the configuration register.
* MX25L12845E/MX25L12865E: These chips don't have the configuration
register.
Tests the write protect functionality on the MX25L12833F chip only.
BUG=b:332486637
TEST=Test flashrom --wp-disable with MX25L12833FZNI-10 on ChromeOS
Change-Id: I379c833eea3ed3487504126f45c6df672a772ddc
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/81792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
---
M flashchips.c
1 file changed, 103 insertions(+), 3 deletions(-)
diff --git a/flashchips.c b/flashchips.c
index 022b18a..373f28c 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -9005,13 +9005,60 @@
{
.vendor = "Macronix",
- .name = "MX25L12833F/MX25L12835F/MX25L12845E/MX25L12865E/MX25L12873F",
+ .name = "MX25L12833F",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX25L12805D,
.total_size = 16384,
.page_size = 256,
- /* OTP: MX25L12833F has 1KB total, others have 512B total; enter 0xB1, exit 0xC1 */
+ /* OTP: 1KB total; enter 0xB1, exit 0xC1 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .tested = TEST_OK_PREWB,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 4096} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 512} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 256} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {16 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {16 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ, /* Fast read (0x0B) supported */
+ .voltage = {2700, 3600},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .tb = {CONFIG, 3, OTP},
+ .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */
+ },
+ .decode_range = DECODE_RANGE_SPI25,
+ },
+
+ {
+ .vendor = "Macronix",
+ .name = "MX25L12835F/MX25L12873F",
+ .bustype = BUS_SPI,
+ .manufacture_id = MACRONIX_ID,
+ .model_id = MACRONIX_MX25L12805D,
+ .total_size = 16384,
+ .page_size = 256,
+ /* OTP: 512B total; enter 0xB1, exit 0xC1 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
@@ -9035,12 +9082,65 @@
.block_erase = SPI_BLOCK_ERASE_C7,
}
},
- /* TODO: security register and SBLK/SBULK; MX25L12835F: configuration register */
.printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */
.unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD,
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ, /* Fast read (0x0B) supported */
.voltage = {2700, 3600},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .tb = {CONFIG, 3, OTP},
+ .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */
+ },
+ .decode_range = DECODE_RANGE_SPI25,
+ },
+
+ {
+ .vendor = "Macronix",
+ .name = "MX25L12845E/MX25L12865E",
+ .bustype = BUS_SPI,
+ .manufacture_id = MACRONIX_ID,
+ .model_id = MACRONIX_MX25L12805D,
+ .total_size = 16384,
+ .page_size = 256,
+ /* OTP: 512B total; enter 0xB1, exit 0xC1 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .tested = TEST_OK_PREW,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 4096} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 512} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 256} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {16 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {16 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ, /* Fast read (0x0B) supported */
+ .voltage = {2700, 3600},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .wps = {SECURITY, 7, OTP}, /* This bit is set by WPSEL command */
+ },
+ .decode_range = DECODE_RANGE_SPI25,
},
{
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