Edward O'Callaghan has uploaded this change for review.

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jedec.c: Move probe_timings decode into sep func

Change-Id: I638518cd537954172eb774f6d15af0db7e06d1ba
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M jedec.c
1 file changed, 29 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/09/72609/1

diff --git a/jedec.c b/jedec.c
index 3df9cf2..b90454d 100644
--- a/jedec.c
+++ b/jedec.c
@@ -165,6 +165,24 @@
 	return 1;
 }
 
+static int probe_timings(const struct flashchip *chip, unsigned int *tenter, unsigned int *texit)
+{
+	if (chip->probe_timing > 0) {
+		*tenter = *texit = chip->probe_timing;
+	} else if (chip->probe_timing == TIMING_ZERO) { /* No delay. */
+		*tenter = *texit = 0;
+	} else if (chip->probe_timing == TIMING_FIXME) { /* == _IGNORED */
+		msg_cdbg("Chip lacks correct probe timing information, using default 10ms/40us. ");
+		*tenter = 10000;
+		*texit = 40;
+	} else {
+		msg_cerr("Chip has negative value in probe_timing, failing without chip access\n");
+		return -1;
+	}
+
+	return 0;
+}
+
 int probe_jedec(struct flashctx *flash)
 {
 	const chipaddr bios = flash->virtual_memory;
@@ -176,18 +194,8 @@
 	uint32_t flashcontent1, flashcontent2;
 	unsigned int probe_timing_enter, probe_timing_exit;
 
-	if (chip->probe_timing > 0)
-		probe_timing_enter = probe_timing_exit = chip->probe_timing;
-	else if (chip->probe_timing == TIMING_ZERO) { /* No delay. */
-		probe_timing_enter = probe_timing_exit = 0;
-	} else if (chip->probe_timing == TIMING_FIXME) { /* == _IGNORED */
-		msg_cdbg("Chip lacks correct probe timing information, using default 10ms/40us. ");
-		probe_timing_enter = 10000;
-		probe_timing_exit = 40;
-	} else {
-		msg_cerr("Chip has negative value in probe_timing, failing without chip access\n");
+	if (probe_timings(chip, &probe_timing_enter, &probe_timing_exit) < 0)
 		return 0;
-	}
 
 	/* Earlier probes might have been too fast for the chip to enter ID
 	 * mode completely. Allow the chip to finish this before seeing a

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