Sergii Dmytruk has uploaded this change for review.

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spi25_statusreg.c: add SR3 read/write support

Adds support for reading and writing the third status register, which
needs to be enabled per chip.

Extended WRSR doesn't cover SR3, so only one feature flag is added.

Change-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
---
M flash.h
M spi.h
M spi25_statusreg.c
3 files changed, 21 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/30/60230/1

diff --git a/flash.h b/flash.h
index d9b8d3a..16a31ed 100644
--- a/flash.h
+++ b/flash.h
@@ -144,6 +144,8 @@
 #define FEATURE_WRSR2		(1 << 20)
 #define FEATURE_RDSR2		(1 << 21)
 
+/* Status register 3 can be read and written. */
+#define FEATURE_SR3		(1 << 22)
 
 #define ERASED_VALUE(flash)	(((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)
 
@@ -175,9 +177,10 @@
 	INVALID_REG = 0,
 	STATUS1,
 	STATUS2,
+	STATUS3,
 	CONFIG1,
 };
-#define MAX_REGISTERS 4
+#define MAX_REGISTERS 5
 
 struct reg_bit_info {
 	/* Register containing the bit */
diff --git a/spi.h b/spi.h
index 845b6c2..14f71aa 100644
--- a/spi.h
+++ b/spi.h
@@ -136,6 +136,11 @@
 #define JEDEC_RDSR2_OUTSIZE	0x01
 #define JEDEC_RDSR2_INSIZE	0x01
 
+/* Read Status Register 3 */
+#define JEDEC_RDSR3		0x15
+#define JEDEC_RDSR3_OUTSIZE	0x01
+#define JEDEC_RDSR3_INSIZE	0x01
+
 /* Status Register Bits */
 #define SPI_SR_WIP	(0x01 << 0)
 #define SPI_SR_WEL	(0x01 << 1)
@@ -158,6 +163,11 @@
 #define JEDEC_WRSR2_OUTSIZE	0x02
 #define JEDEC_WRSR2_INSIZE	0x00
 
+/* Write Status Register 3 */
+#define JEDEC_WRSR3		0x11
+#define JEDEC_WRSR3_OUTSIZE	0x02
+#define JEDEC_WRSR3_INSIZE	0x00
+
 /* Enter 4-byte Address Mode */
 #define JEDEC_ENTER_4_BYTE_ADDR_MODE	0xB7
 
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 6f804b1..c4d7399 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -26,6 +26,7 @@
 	switch (reg) {
 	case STATUS1:	return "SR1";
 	case STATUS2:	return "SR2";
+	case STATUS3:	return "SR3";
 	case CONFIG1:	return "CR1";
 	default:	return "Unknown register";
 	}
@@ -63,6 +64,10 @@
 			write_cmd[2] = value;
 			write_cmd_len = JEDEC_WRSR_EXT_OUTSIZE;
 		}
+	} else if (reg == STATUS3 && (feature_bits & FEATURE_SR3)) {
+		write_cmd[0] = JEDEC_WRSR3;
+		write_cmd[1] = value;
+		write_cmd_len = JEDEC_WRSR3_OUTSIZE;
 	}
 
 	if (write_cmd_len == 0) {
@@ -136,6 +141,8 @@
 		read_cmd = JEDEC_RDSR;
 	} else if (reg == STATUS2 && (feature_bits & FEATURE_RDSR2)) {
 		read_cmd = JEDEC_RDSR2;
+	} else if (reg == STATUS3 && (feature_bits & FEATURE_SR3)) {
+		read_cmd = JEDEC_RDSR3;
 	} else {
 		msg_cerr("Chip does not support reading register %s.\n", reg_name(reg));
 		return 1;

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