Luc Verhaegen has uploaded this change for review.

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ati: add rv730/rv740 support

For some reason, the pcie clk divider also gets set...

TODO: verify on real hw whether this actually is needed.

Change-Id: I0b6abc817c7ba0f12adc94c07bf81de118adffe5
Signed-off-by: Luc Verhaegen <libv@skynet.be>
---
M ati_spi.c
1 file changed, 39 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/93/29093/1

diff --git a/ati_spi.c b/ati_spi.c
index 87fe2d1..56246eb 100644
--- a/ati_spi.c
+++ b/ati_spi.c
@@ -31,6 +31,10 @@
 struct ati_spi_pci_private {
 	int io_bar;
 
+#define ATI_SPI_TYPE_R600	1
+#define ATI_SPI_TYPE_RV730	2
+	int type;
+
 	int (*save) (struct flashrom_pci_device *device);
 	int (*restore) (struct flashrom_pci_device *device);
 	int (*enable) (struct flashrom_pci_device *device);
@@ -170,12 +174,17 @@
 static int
 r600_spi_enable(struct flashrom_pci_device *device)
 {
+	const struct ati_spi_pci_private *private = device->private;
 	int i;
 
 	msg_pdbg("%s();\n", __func__);
 
-	/* software enable clock gating and set sck divider to 1 */
-	mmio_mask(R600_ROM_CNTL, 0x10000002, 0xF0000002);
+	if (private->type == ATI_SPI_TYPE_RV730)
+		/* As below, but also set the (unused?) pcie clk divider */
+		mmio_mask(R600_ROM_CNTL, 0x19000002, 0xFF000002);
+	else
+		/* software enable clock gating and set sck divider to 1 */
+		mmio_mask(R600_ROM_CNTL, 0x10000002, 0xF0000002);
 
 	/* set gpio7,8,9 low */
 	mmio_mask(R600_GPIOPAD_A, 0, 0x0700);
@@ -324,6 +333,19 @@
  */
 static const struct ati_spi_pci_private r600_spi_pci_private = {
 	.io_bar = 2,
+	.type = ATI_SPI_TYPE_R600,
+	.save = r600_spi_save,
+	.restore = r600_spi_restore,
+	.enable = r600_spi_enable,
+	.master = &r600_spi_master,
+};
+
+/*
+ * Used by RV730/RV740.
+ */
+static const struct ati_spi_pci_private rv730_spi_pci_private = {
+	.io_bar = 2,
+	.type = ATI_SPI_TYPE_RV730,
 	.save = r600_spi_save,
 	.restore = r600_spi_restore,
 	.enable = r600_spi_enable,
@@ -356,6 +378,21 @@
 	{0x1002, 0x9460, NT, &r600_spi_pci_private},
 	{0x1002, 0x9462, NT, &r600_spi_pci_private},
 	{0x1002, 0x946A, NT, &r600_spi_pci_private},
+	{0x1002, 0x9480, NT, &rv730_spi_pci_private},
+	{0x1002, 0x9488, NT, &rv730_spi_pci_private},
+	{0x1002, 0x9489, NT, &rv730_spi_pci_private},
+	{0x1002, 0x9490, NT, &rv730_spi_pci_private},
+	{0x1002, 0x9491, NT, &rv730_spi_pci_private},
+	{0x1002, 0x9495, NT, &rv730_spi_pci_private},
+	{0x1002, 0x9498, NT, &rv730_spi_pci_private},
+	{0x1002, 0x949C, NT, &rv730_spi_pci_private},
+	{0x1002, 0x949E, NT, &rv730_spi_pci_private},
+	{0x1002, 0x949F, NT, &rv730_spi_pci_private},
+	{0x1002, 0x94A0, NT, &rv730_spi_pci_private},
+	{0x1002, 0x94A1, NT, &rv730_spi_pci_private},
+	{0x1002, 0x94A3, NT, &rv730_spi_pci_private},
+	{0x1002, 0x94B3, NT, &rv730_spi_pci_private},
+	{0x1002, 0x94B4, NT, &rv730_spi_pci_private},
 	{0x1002, 0x94C1, NT, &r600_spi_pci_private},
 	{0x1002, 0x94C3, NT, &r600_spi_pci_private},
 	{0x1002, 0x94C4, NT, &r600_spi_pci_private},

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