Edward O'Callaghan has uploaded this change for review.

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superio/: Pass flashprog to drv init() entry

MAYBE needed to remove singletons.

Change-Id: I81f39789152ac6d44a44197fa25154597e8855fa
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M include/programmer.h
M internal.c
M it87spi.c
3 files changed, 18 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/18/72818/1

diff --git a/include/programmer.h b/include/programmer.h
index b4a4cfb..4e8aedd 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -372,7 +372,7 @@
 void enter_conf_mode_ite(uint16_t port);
 void exit_conf_mode_ite(uint16_t port);
 void probe_superio_ite(void);
-int init_superio_ite(const struct programmer_cfg *cfg);
+int init_superio_ite(struct flashrom_programmer *, const struct programmer_cfg *cfg);
 
 /* trivial wrapper to avoid cluttering internal_init() with #if */
 static inline int try_mtd(struct flashrom_programmer *flashprog, const struct programmer_cfg *cfg)
diff --git a/internal.c b/internal.c
index 0928f6e..654f696 100644
--- a/internal.c
+++ b/internal.c
@@ -270,7 +270,7 @@
 #if defined(__i386__) || defined(__x86_64__)
 	/* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and
 	 * parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */
-	init_superio_ite(cfg);
+	init_superio_ite(flashprog, cfg);
 
 	if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model, force_boardenable)) {
 		msg_perr("Aborting to be safe.\n");
diff --git a/it87spi.c b/it87spi.c
index 1820ef4..1f38336 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -324,7 +324,7 @@
 	.probe_opcode	= default_spi_probe_opcode,
 };
 
-static uint16_t it87spi_probe(const struct programmer_cfg *cfg, uint16_t port)
+static uint16_t it87spi_probe(struct flashrom_programmer *flashprog, const struct programmer_cfg *cfg, uint16_t port)
 {
 	uint8_t tmp = 0;
 	uint16_t flashport = 0;
@@ -440,10 +440,10 @@
 	if (internal_buses_supported & BUS_SPI)
 		msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
 	/* FIXME: Add the SPI bus or replace the other buses with it? */
-	return register_spi_master(NULL, &spi_master_it87xx, data); /* FIXME(quasisec): pass flashprog. */
+	return register_spi_master(flashprog, &spi_master_it87xx, data);
 }
 
-int init_superio_ite(const struct programmer_cfg *cfg)
+int init_superio_ite(struct flashrom_programmer *flashprog, const struct programmer_cfg *cfg)
 {
 	int i;
 	int ret = 0;
@@ -461,7 +461,7 @@
 		case 0x8718:
 		case 0x8720:
 		case 0x8728:
-			ret |= it87spi_probe(cfg, superios[i].port);
+			ret |= it87spi_probe(flashprog, cfg, superios[i].port);
 			break;
 		default:
 			msg_pdbg2("Super I/O ID 0x%04hx is not on the list of flash-capable controllers.\n",

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