Attention is currently required from: Patrick Georgi, Rizwan Qureshi, Stefan Reinauer, Sridhar Siricilla, Angel Pons, Alex Levin, YH Lin, Martin Roth, Subrata Banik, Caveh Jalali, Tim Wawrzynczak, Nick Vaccaro, Boris Mittelberg.

Patch set 7:Code-Review +1

6 comments:

Commit Message:
- Patch Set #7, Line 17:
```
Without this synchronisation being implemented, flashrom is running
into below error:

Erasing and writing flash chip... Timeout error between offset
0x0061c000 and 0x0061c03f (= 0x0061c000 + 63)! FAILED!
Uh oh. Erase/write failed. Checking if anything has changed.
```
  If you want to mention this, please also describe the full setup,
  preferably how to reproduce the error. And also that it's not con-
  sidered a valid use case.
- Patch Set #7, Line 24: BUG=b:215255210
  What's said in this issue and what's its status?
- Patch Set #7, Line 25: TEST=Concurrent flashrom access is not throwing timeout.
  Please also test that things still work on as many platforms as
  possible starting with ICH9.
Patchset:
- Patch Set #2:
  > If there is a Hardware Sequencing Cycle In Progress and an attempt is made to program any of the c […]
  Resolving, discussion seems settled.
Patchset:
- Patch Set #6:
  A version of this change that takes the applicable context into account
  (e.g. other waiting loops in this driver, implications when multiple
  instances would reach this point in the code simultaneously) would be
  accepted immediately.
  I understand that would be a comprehensive fix across flashrom.
  Doesn't need to be. All I'm asking for is to keep the whole code sound
  and not just the single spot where a check would be added. This could
  for instance be a simple
```
  if (REGREAD8(ICH9_REG_HSFS) & HSFS_SCIP)
          return -1;
```
  Implemented the same with current patchset. please help to take a look (if possible)
  Ack
File ichspi.c:
- Patch Set #7, Line 1410: Error: SCIP never cleared!
  Maybe this would fit better:
```
  Error: SCIP bit is unexpectedly set.
```

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