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4 comments:

• File ite_ec.c:

  • Patch Set #9, Line 176: ctx_data->control_port = EC_CONTROL;

    CMD,not CONTROL

    Done

• File ite_ec.c:

  • Patch Set #10, Line 211: 0x10

    ec ram `ADP`

  • Patch Set #10, Line 781:

    
    	if (!ec_write_reg(0xf9, 0x20, EC_MAX_STATUS_CHECKS) ||
    	    !ec_write_reg(0xfa, 0x02, EC_MAX_STATUS_CHECKS) ||
    	    !ec_write_reg(0xfb, 0x00, EC_MAX_STATUS_CHECKS) ||
    	    !ec_write_reg(0xf8, 0xb1, EC_MAX_STATUS_CHECKS)) {
    		msg_perr("Unable to initialize controller.\n");
    		return 1;
    

    how could this ever work? o.O https://review.coreboot.org/c/flashrom/+/55714/4/acpi_ec.c#95 […]

    Done

• File ite_ec.c:

  • Patch Set #11, Line 735:

    	if (!ec_write_reg(0xf9, 0x20, EC_MAX_STATUS_CHECKS) ||
    	    !ec_write_reg(0xfa, 0x02, EC_MAX_STATUS_CHECKS) ||
    	    !ec_write_reg(0xfb, 0x00, EC_MAX_STATUS_CHECKS) ||
    	    !ec_write_reg(0xf8, 0xb1, EC_MAX_STATUS_CHECKS)) {
    		msg_perr("Unable to initialize controller.\n");
    		return 1;
    	}
    
    

    I found out what this does:
    The registers are FCMD,FDAT,FBUF,FBF1 (0xf8-0xfb) in the operation region RAM1.
    Wth FCMD 0xb1 one can read registers / external RAM (XDATA), code, flash (via indirect flash registers ECIN*), or IDATA/RAM depending on FBF1, where (FBF1 & 0x0f) is the length and (FBF1 & 0xf0) is the type (XDATA, code, ....).

    In this case this means:
    FBF1=0x00 reads 1 byte (yes, 0x*0 gets increased by 1) of XDATA
    FDAT:FBUF form the 16bit XDATA address (DPTR); 0x2002 is register CHIPVER
    The result gets stored in FDAT and can be read by the host, which is done here in line #157.

    So, the code reads CHIPVER, where the upper nibble encodes the block count / rom size.
    The code from lines 735++ should go to line 157 and maybe that whole rom size code should probably become a separate function. Also, please add comments what the code does, now that we know it.

    The error message needs to be adapted to sth like "unable to read block count / rom size".

    Fun fact: CHIPVER could be read from the super io cfg registers as well (register 0x22) according to the datasheet.

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