Nico Huber merged this change.

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Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved David Hendricks: Looks good to me, approved
vt_vx: check whether the chipset's MMIO range is configured

Avoid attempting to read the SPI bases from the location 0x00000000, all
zeroes mean that the chipset's MMIO area is not enabled.

Change-Id: I5d3a1ba695153e854e0979ae634f8ed97e6b6293
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/23029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
---
M chipset_enable.c
1 file changed, 8 insertions(+), 0 deletions(-)

diff --git a/chipset_enable.c b/chipset_enable.c
index a499ba0..5716ebf 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1013,10 +1013,18 @@
switch(dev->device_id) {
case 0x8353: /* VX800/VX820 */
spi0_mm_base = pci_read_long(dev, 0xbc) << 8;
+ if (spi0_mm_base == 0x0) {
+ msg_pdbg ("MMIO not enabled!\n");
+ return ERROR_FATAL;
+ }
break;
case 0x8409: /* VX855/VX875 */
case 0x8410: /* VX900 */
mmio_base = pci_read_long(dev, 0xbc) << 8;
+ if (mmio_base == 0x0) {
+ msg_pdbg ("MMIO not enabled!\n");
+ return ERROR_FATAL;
+ }
mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN);
if (mmio_base_physmapped == ERROR_PTR)
return ERROR_FATAL;

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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I5d3a1ba695153e854e0979ae634f8ed97e6b6293
Gerrit-Change-Number: 23029
Gerrit-PatchSet: 2
Gerrit-Owner: Lubomir Rintel <lkundrak@v3.sk>
Gerrit-Reviewer: David Hendricks <david.hendricks@gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h@gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>