Edward O'Callaghan has uploaded this change for review.
ichspi: WIP Move global state into spi_master 'data' field
NOT-FOR-MERGE-YET.
Change-Id: I368846039445f5e52a7c84a91676ee13b4aab9be
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M ichspi.c
1 file changed, 42 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/04/43504/1
diff --git a/ichspi.c b/ichspi.c
index b90b864..19ce8cf 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -239,6 +239,10 @@
static void *ich_spibar = NULL;
+struct ich_spi_data {
+ enum ich_chipset ich_gen;
+};
+
typedef struct _OPCODE {
uint8_t opcode; //This commands spi opcode
uint8_t spi_type; //This commands spi type
@@ -494,7 +498,7 @@
return 0xFF;
}
-static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
+static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt, enum ich_chipset ich_gen)
{
uint8_t spi_type;
@@ -524,7 +528,7 @@
int oppos = 2; // use original JEDEC_BE_D8 offset
curopcodes->opcode[oppos].opcode = opcode;
curopcodes->opcode[oppos].spi_type = spi_type;
- program_opcodes(curopcodes, 0, ich_generation);
+ program_opcodes(curopcodes, 0, ich_gen);
oppos = find_opcode(curopcodes, opcode);
msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
return oppos;
@@ -1079,8 +1083,11 @@
{
/* max_data_read == max_data_write for all Intel/VIA SPI masters */
uint8_t maxlength = flash->mst->spi.max_data_read;
+ const struct ich_spi_data *ich_data =
+ (const struct ich_spi_data *)flash->mst->spi.data;
+ enum ich_chipset ich_gen = ich_data->ich_gen;
- if (ich_generation == CHIPSET_ICH_UNKNOWN) {
+ if (ich_gen == CHIPSET_ICH_UNKNOWN) {
msg_perr("%s: unsupported chipset\n", __func__);
return -1;
}
@@ -1092,7 +1099,7 @@
return SPI_INVALID_LENGTH;
}
- switch (ich_generation) {
+ switch (ich_gen) {
case CHIPSET_ICH7:
case CHIPSET_TUNNEL_CREEK:
case CHIPSET_CENTERTON:
@@ -1115,12 +1122,15 @@
uint32_t addr = 0;
uint8_t *data;
int count;
+ const struct ich_spi_data *ich_data =
+ (const struct ich_spi_data *)flash->mst->spi.data;
+ enum ich_chipset ich_gen = ich_data->ich_gen;
/* find cmd in opcodes-table */
opcode_index = find_opcode(curopcodes, cmd);
if (opcode_index == -1) {
if (!ichspi_lock)
- opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
+ opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt, ich_gen);
if (opcode_index == SPI_INVALID_LENGTH) {
msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd);
return SPI_INVALID_LENGTH;
@@ -1380,6 +1390,9 @@
uint32_t erase_block;
uint16_t hsfc;
uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */
+ const struct ich_spi_data *ich_data =
+ (const struct ich_spi_data *)flash->mst->spi.data;
+ enum ich_chipset ich_gen = ich_data->ich_gen;
erase_block = ich_hwseq_get_erase_block_size(addr);
if (len != erase_block) {
@@ -1416,10 +1429,10 @@
hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
hsfc |= HSFC_FGO; /* start */
msg_pdbg("HSFC used for block erasing: ");
- prettyprint_ich9_reg_hsfc(hsfc, ich_generation);
+ prettyprint_ich9_reg_hsfc(hsfc, ich_gen);
REGWRITE16(ICH9_REG_HSFC, hsfc);
- if (ich_hwseq_wait_for_cycle_complete(timeout, len, ich_generation))
+ if (ich_hwseq_wait_for_cycle_complete(timeout, len, ich_gen))
return -1;
return 0;
}
@@ -1430,6 +1443,9 @@
uint16_t hsfc;
uint16_t timeout = 100 * 60;
uint8_t block_len;
+ const struct ich_spi_data *ich_data =
+ (const struct ich_spi_data *)flash->mst->spi.data;
+ enum ich_chipset ich_gen = ich_data->ich_gen;
if (addr + len > flash->chip->total_size * 1024) {
msg_perr("Request to read from an inaccessible memory address "
@@ -1456,7 +1472,7 @@
hsfc |= HSFC_FGO; /* start */
REGWRITE16(ICH9_REG_HSFC, hsfc);
- if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation))
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_gen))
return 1;
ich_read_data(buf, block_len, ICH9_REG_FDATA0);
addr += block_len;
@@ -1471,6 +1487,9 @@
uint16_t hsfc;
uint16_t timeout = 100 * 60;
uint8_t block_len;
+ const struct ich_spi_data *ich_data =
+ (const struct ich_spi_data *)flash->mst->spi.data;
+ enum ich_chipset ich_gen = ich_data->ich_gen;
if (addr + len > flash->chip->total_size * 1024) {
msg_perr("Request to write to an inaccessible memory address "
@@ -1498,7 +1517,7 @@
hsfc |= HSFC_FGO; /* start */
REGWRITE16(ICH9_REG_HSFC, hsfc);
- if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_generation))
+ if (ich_hwseq_wait_for_cycle_complete(timeout, block_len, ich_gen))
return -1;
addr += block_len;
buf += block_len;
@@ -1539,7 +1558,7 @@
* No need to bother with fixups.
*/
if (!ichspi_lock) {
- oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
+ oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt, ich_gen);
if (oppos == -1)
continue;
curopcodes->opcode[oppos].atomic = preoppos + 1;
@@ -1686,7 +1705,7 @@
msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
}
-static const struct spi_master spi_master_ich7 = {
+static struct spi_master spi_master_ich7 = {
.max_data_read = 64,
.max_data_write = 64,
.command = ich_spi_send_command,
@@ -1696,7 +1715,7 @@
.write_aai = default_spi_write_aai,
};
-static const struct spi_master spi_master_ich9 = {
+static struct spi_master spi_master_ich9 = {
.max_data_read = 64,
.max_data_write = 64,
.command = ich_spi_send_command,
@@ -1733,6 +1752,16 @@
ich_generation = ich_gen;
ich_spibar = spibar;
+ struct ich_spi_data *ich_data = calloc(1, sizeof(struct ich_spi_data));
+ if (!ich_data) {
+ msg_perr("Unable to allocate space for extra SPI master data.\n");
+ return SPI_GENERIC_ERROR;
+ }
+
+ ich_data->ich_gen = ich_gen;
+ spi_master_ich7.data = ich_data;
+ spi_master_ich9.data = ich_data;
+ spi_master_via.data = ich_data;
memset(&desc, 0x00, sizeof(struct ich_descriptors));
@@ -2046,7 +2075,7 @@
return 0;
}
-static const struct spi_master spi_master_via = {
+static struct spi_master spi_master_via = {
.max_data_read = 16,
.max_data_write = 16,
.command = ich_spi_send_command,
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