Kapil Porwal has uploaded this change for review.

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flashchips.c: Add reg_bits for W25Q256JW

Add reg_bits for W25Q256JW as per the datasheet. The register
definitions are same as W25Q256JW_DTR.

BUG=none

Change-Id: I050754b28a90911a50f891869297524ce9a6720e
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
---
M flashchips.c
1 file changed, 13 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/23/85323/1

diff --git a/flashchips.c b/flashchips.c
index 0e83200..ff2d834 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -20336,8 +20336,9 @@
 		.page_size	= 256,
 		/* supports SFDP */
 		/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
-		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
-		.tested		= TEST_OK_PREW,
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2
+				  | FEATURE_WRSR3,
+		.tested		= TEST_OK_PREWB,
 		.probe		= PROBE_SPI_RDID,
 		.probe_timing	= TIMING_ZERO,
 		.block_erasers	=
@@ -20370,6 +20371,16 @@
 		.write		= SPI_CHIP_WRITE256,
 		.read		= SPI_CHIP_READ,
 		.voltage	= {1650, 1950},
+		.reg_bits	=
+		{
+			.srp	= {STATUS1, 7, RW},
+			.srl	= {STATUS2, 0, RW},
+			.bp	= {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+			.tb	= {STATUS1, 6, RW},
+			.cmp	= {STATUS2, 6, RW},
+			.wps	= {STATUS3, 2, RW},
+		},
+		.decode_range	= DECODE_RANGE_SPI25,
 	},
 
 	{

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