ichspi: Fix number of bytes for read, write, flash id, erase operation

This patch fixes a potential issue where the SPI controller register
HSFC.FDBC (bits 24-29) value gets incorrectly calculated while passing
the `len` as `0` instead of `1`.

As per Intel EDS, `0b` in the FDBC represents 1 byte while `0x3f`
represents 64-bytes to be transferred. The number of bytes
transferred is the value of this field plus 1.

If we would like to transfer 1 byte then we need to set `0b` in
FDBC for operations like read, write, flash id as to account for
`set byte count` hence, the `len` argument should be `1`.

Additionally, as per EDS, the FDBC field is ignored for any block
erase command.

Note: `FDBC` field still holds the non-zero default value before
any HW seq operation (which might impact the HW seq operations unless
cleared explicitly). An incremental patch on this train will fix
that observation too.

BUG=b:258280679
TEST=Able to build flashrom and perform below operations on Google,
Rex and Google, Kano/Taeko.

Without this patch:

HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x3f00
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (--wp-disable): 0x3f11

With this patch:

HSFC register value inside ich_start_hwseq_xfer() before initiating
the HW seq operations: 0x300
HSFC register value inside ich_start_hwseq_xfer() during the HW seq
operations (--wp-disable): 0x311

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie5de7c5bd9809d146a317df56996f7f8a85ca9a5
---
M ichspi.c
1 file changed, 51 insertions(+), 3 deletions(-)