Sophie van Soest has uploaded this change for review.

View Change

Enabled Chipset it97spi: 0x8620 Gigabyte-Z97-HD3

Added missing address: 0x8620 for the it97 to use the parameter dualbootbios.
Marked Z97 as OK.

Dumped and verified both bios.

Signed-off-by: Sophie van Soest <sophie@entropie.rocks>
Change-Id: I0be9effe4a2f1f9699e016c7fc45018c9c522cbc
---
M chipset_enable.c
M it87spi.c
2 files changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/55/56055/1

diff --git a/chipset_enable.c b/chipset_enable.c
index cdd51ae..2540692 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1969,7 +1969,7 @@
 	{0x8086, 0x8cc1, B_FS,   NT,  "Intel", "9 Series",			enable_flash_pch9},
 	{0x8086, 0x8cc2, B_FS,   NT,  "Intel", "9 Series Engineering Sample",	enable_flash_pch9},
 	{0x8086, 0x8cc3, B_FS,   NT,  "Intel", "9 Series",			enable_flash_pch9},
-	{0x8086, 0x8cc4, B_FS,   NT,  "Intel", "Z97",				enable_flash_pch9},
+	{0x8086, 0x8cc4, B_FS,   OK,  "Intel", "Z97",				enable_flash_pch9},
 	{0x8086, 0x8cc6, B_FS,   NT,  "Intel", "H97",				enable_flash_pch9},
 	{0x8086, 0x8d40, B_FS,   NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
 	{0x8086, 0x8d41, B_FS,   NT,  "Intel", "C610/X99 (Wellsburg)",		enable_flash_pch8_wb},
diff --git a/it87spi.c b/it87spi.c
index cbf830b..8490bdd 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -454,6 +454,7 @@
 		case 0x8705:
 			ret |= it8705f_write_enable(superios[i].port);
 			break;
+		case 0x8620:
 		case 0x8716:
 		case 0x8718:
 		case 0x8720:

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