Edward O'Callaghan has uploaded this change for review.

View Change

ichspi.c: WIP Put ich_spibar inside spi_master data feild

Change-Id: I74469a48420eff9ef4f07040dcb2d297143859df
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M ichspi.c
1 file changed, 10 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/07/43507/1

diff --git a/ichspi.c b/ichspi.c
index 661236e..4ea80c8 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -240,6 +240,7 @@
 
 struct ich_spi_data {
 	enum ich_chipset ich_gen;
+	void *ich_spibar;
 };
 
 typedef struct _OPCODE {
@@ -1753,7 +1754,6 @@
 	} ich_spi_mode = ich_auto;
 	size_t num_freg, num_pr, reg_pr0;
 
-	ich_spibar = spibar;
 	struct ich_spi_data *ich_data = calloc(1, sizeof(struct ich_spi_data));
 	if (!ich_data) {
 		msg_perr("Unable to allocate space for extra SPI master data.\n");
@@ -1761,6 +1761,7 @@
 	}
 
 	ich_data->ich_gen = ich_gen;
+	ich_data->ich_spibar = spibar;
 	spi_master_ich7.data = ich_data;
 	spi_master_ich9.data = ich_data;
 
@@ -2098,13 +2099,6 @@
 	/* Not sure if it speaks all these bus protocols. */
 	internal_buses_supported &= BUS_LPC | BUS_FWH;
 
-	struct ich_spi_data ich_data = {
-		.ich_gen = CHIPSET_ICH7,
-	};
-	spi_master_via.data = &ich_data;
-
-	register_spi_master(&spi_master_via);
-
 	msg_pdbg("0x00: 0x%04x     (SPIS)\n", mmio_readw(ich_spibar + 0));
 	msg_pdbg("0x02: 0x%04x     (SPIC)\n", mmio_readw(ich_spibar + 2));
 	msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
@@ -2135,9 +2129,17 @@
 		ichspi_lock = 1;
 	}
 
+	struct ich_spi_data ich_data = {
+		.ich_gen = CHIPSET_ICH7,
+		.ich_spibar = ich_spibar,
+	};
+	spi_master_via.data = &ich_data;
+
 	ich_set_bbar(0, ich_data.ich_gen);
 	ich_init_opcodes(ich_data.ich_gen);
 
+	register_spi_master(&spi_master_via);
+
 	return 0;
 }
 

To view, visit change 43507. To unsubscribe, or for help writing mail filters, visit settings.