Attention is currently required from: Anton Samsonov.
Anton Samsonov would like Anton Samsonov to review this change.
flashchips: Add Spansion S25FS512S
Tested probe, read, erase, write on FS512SAIF01 chips
using Linux SPI and DediProg SF100 programmers.
This change affects S25FL512S identification as well,
so that both chips can be unambiguously detected by probing.
Datasheets used:
* Infineon-S25FS512S_512_Mb_1-DataSheet-v16_00-EN.pdf
at https://www.infineon.com/dgdl/?fileId=8ac78c8c7d0d8da4017d0ed681a356fe
* Infineon-S25FL512S_512_Mb_64_MB_FL-S_Flash_SPI_Multi-I_O_3-DataSheet-v21_00-EN.pdf
at https://www.infineon.com/dgdl/?fileId=8ac78c8c7d0d8da4017d0ed046ae4b53
Change-Id: I40b6c081ec7d57eac4f6d2b69cea3878bc92bb47
Signed-off-by: Anton Samsonov <devel@zxlab.ru>
---
M flashchips.c
M include/flashchips.h
M s25f.c
3 files changed, 52 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/85/85585/1
diff --git a/flashchips.c b/flashchips.c
index 0e83200..3695622 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -19334,7 +19334,7 @@
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP |
FEATURE_4BA_NATIVE | FEATURE_4BA_ENTER_EAR7 | FEATURE_4BA_EAR_1716,
.tested = TEST_UNTESTED,
- .probe = PROBE_SPI_RDID,
+ .probe = PROBE_SPI_BIG_SPANSION,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
@@ -19422,6 +19422,53 @@
},
{
+ .vendor = "Spansion",
+ .name = "S25FS512S",
+ .bustype = BUS_SPI,
+ .manufacture_id = SPANSION_ID,
+ .model_id = SPANSION_S25FS512S,
+ .total_size = 65536,
+ .page_size = 256, /* 256 or 512 bytes page programming buffer */
+ /* OTP: 1024B total, 32B reserved; read 0x4B; write 0x42 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI |
+ FEATURE_4BA_NATIVE | FEATURE_4BA_ENTER,
+ /* Note on FEATURE_4BA_ENTER: the command set only defines command 0xB7
+ to enter 4BA mode, but there is no counterpart command "Exit 4BA mode",
+ and the code 0xE9 is assigned to another command ("Password unlock"). */
+ /* Note on FEATURE_4BA_ENTER_EAR7 (not set): the "Extended address mode" bit
+ is stored in configuration register CR2V[7], which can only be read / written
+ by generic commands ("Read any register" / "Write any register"), that itself
+ expect a 3- or 4-byte address of register in question, which in turn depends on
+ the same register, that is initially set from non-volatile register CR2NV[7]
+ that defaults to 0, but can be programmed to 1 for starting in 32-bit mode. */
+ .tested = TEST_OK_PREW,
+ .probe = PROBE_SPI_BIG_SPANSION,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { { 256 * 1024, 256} },
+ .block_erase = SPI_BLOCK_ERASE_DC,
+ }, {
+ .eraseblocks = { { 256 * 1024, 256} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { { 65536 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { { 65536 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP2_EP_SRWD, /* TODO: SR2 and many others */
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD, /* TODO: various other locks */
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ,
+ .voltage = {1700, 2000},
+ },
+
+
+ {
.vendor = "SyncMOS/MoselVitelic",
.name = "{F,S,V}29C51001B",
.bustype = BUS_PARALLEL,
diff --git a/include/flashchips.h b/include/flashchips.h
index 0fea690..26cef4f 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -701,7 +701,7 @@
#define SPANSION_S25FL064A 0x0216 /* Same as S25FL064P, but the latter supports EDI and CFI */
#define SPANSION_S25FL128 0x2018 /* Same ID for various S25FL127S, S25FL128P, S25FL128S and S25FL129P (including dual-die S70FL256P) variants (EDI supported) */
#define SPANSION_S25FL256 0x0219
-#define SPANSION_S25FL512 0x0220
+#define SPANSION_S25FL512 0x02200080
#define SPANSION_S25FL204 0x4013
#define SPANSION_S25FL208 0x4014
#define SPANSION_S25FL216 0x4015 /* Same as S25FL216K, but the latter supports OTP, 3 status regs, quad I/O, SFDP etc. */
@@ -714,6 +714,7 @@
#define SPANSION_S25FS128S_S 0x20180181 /* Small sectors. */
#define SPANSION_S25FS256S_L 0x02190081 /* Large sectors. */
#define SPANSION_S25FS256S_S 0x02190181 /* Small sectors. */
+#define SPANSION_S25FS512S 0x02200081 /* Uniform Large (256kB) sectors */
#define SPANSION_S25FL128S_UL 0x20180080 /* Uniform Large (128kB) sectors */
#define SPANSION_S25FL128S_US 0x20180180 /* Uniform Small (64kB) sectors */
#define SPANSION_S25FL256S_UL 0x02190080 /* Uniform Large (128kB) sectors */
diff --git a/s25f.c b/s25f.c
index b0f2438..dc90dc4 100644
--- a/s25f.c
+++ b/s25f.c
@@ -371,10 +371,8 @@
*
* offset value meaning
* 00h 01h Manufacturer ID for Spansion
- * 01h 20h 128 Mb capacity
- * 01h 02h 256 Mb capacity
- * 02h 18h 128 Mb capacity
- * 02h 19h 256 Mb capacity
+ * 01h * Memory interface type (02h, 20h, 40h, 60h)
+ * 02h * Memory capacity (18h = 128 Mb, 19h = 256 Mb, 20h = 512 Mb)
* 03h 4Dh Full size of the RDID output (ignored)
* 04h 00h FS: 256-kB physical sectors
* 04h 01h FS: 64-kB physical sectors
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