Attention is currently required from: Anastasia Klimchuk, David Wu, Kapil Porwal, Maximilian Brune, Nikolai Artemiev, Subrata Banik, Tyler Wang.
1 comment:
File flashchips.c:
Patch Set #9, Line 6559: FEATURE_WRSR_EXT2
So the question is between `FEATURE_WRSR_EXT2` and `FEATURE_WRSR2`. […]
I tried to learn from the current code and Nikolai's first commit: https://review.coreboot.org/c/flashrom/+/58570
Here's my understanding:
There are two way of implemention write to status register 2:
---
#### 1. FEATURE_WRSR2：
See the code piece:
```
if (feature_bits & FEATURE_WRSR2) {
write_cmd[0] = JEDEC_WRSR2;
write_cmd[1] = value;
write_cmd_len = JEDEC_WRSR2_OUTSIZE;
break;
}
```
This means that it has seperated instruction to write SR2, take AT25SL128A as an example, see datasheet: https://pdf1.alldatasheet.com/datasheet-pdf/download/1283751/DIALOG/AT25SL128A.html
Page 21 (7.7 Write Status Register-2 (31h)) explicitly describe that they have 0x31 (JEDEC_WRSR2, see include/spi.h) to write SR2.
---
#### 2. FEATURE_WRSR_EXT2 (was FEATURE_WRSR_EXT)
See the code piece:
```
if (feature_bits & FEATURE_WRSR_EXT) {
/*
* Writing SR2 with an extended WRSR command requires
* writing SR1 along with SR2, so just read SR1 and
* write it back
*/
uint8_t sr1;
if (spi_read_register(flash, STATUS1, &sr1)) {
msg_cerr("Writing SR2 failed: failed to read SR1 for writeback.\n");
return 1;
}
write_cmd[0] = JEDEC_WRSR;
write_cmd[1] = sr1;
write_cmd[2] = value;
write_cmd_len = JEDEC_WRSR_EXT_OUTSIZE;
break;
}
```It means it concat the SR2 after SR1, and if we take a look at GD25LQ255E datasheet (https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20221129/DS-00562-GD25LQ255E-Rev1.1.pdf), page 18 table 10:
Write Status Register 1&2:
We can see that GD25LQ255E support that concat SR 2 value directly after SR 1 value, which aligns with our FEATURE_WRSR_EXT2.
---
Similarly, we could see that W25Q512NW datasheet: https://www.mouser.com/datasheet/2/949/Winbond_07022021_W25Q512NW-2451091.pdf)) is FEATURE_WRSR3 since 8.2.5 (page 33) shows that it has Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) and S25FL128L datasheet: https://www.infineon.com/dgdl/Infineon-S25FL256L_S25FL128L_256-MB_(32-MB)_128-MB_(16-MB)_3.0_V_FL-L_FLASH_MEMORY-DataSheet-v09_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ed40e335224 is FEATURE_WRSR_EXT3 since 8.3.4 (page 81) shows that they just concat SR2, SR3 after SR1 while writing.
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