Edward O'Callaghan has uploaded this change for review.

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it87spi.c: Plumb board_cfg to it8705f_write_enable() entry

Change-Id: Ia48d4d4acd02550c72ee46bfe4042b3c75941da0
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M board_enable.c
M include/programmer.h
M it87spi.c
3 files changed, 13 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/63/73463/1
diff --git a/board_enable.c b/board_enable.c
index d9af44e..1ed1c5d 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -601,7 +601,7 @@
* Suited for all boards with ITE IT8705F.
* The SIS950 Super I/O probably requires a similar flash write enable.
*/
-int it8705f_write_enable(uint8_t port)
+int it8705f_write_enable(struct board_cfg *bcfg, uint8_t port)
{
uint8_t tmp;
int ret = 0;
diff --git a/include/programmer.h b/include/programmer.h
index e81d3bd..97c5e81 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -231,7 +231,7 @@
void w836xx_ext_enter(uint16_t port);
void w836xx_ext_leave(uint16_t port);
void probe_superio_winbond(void);
-int it8705f_write_enable(uint8_t port);
+int it8705f_write_enable(struct board_cfg *bcfg, uint8_t port);
uint8_t sio_read(uint16_t port, uint8_t reg);
void sio_write(uint16_t port, uint8_t reg, uint8_t data);
void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
diff --git a/it87spi.c b/it87spi.c
index 9c64659..dd9ab71 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -452,7 +452,7 @@

switch (superios[i].model) {
case 0x8705:
- ret |= it8705f_write_enable(superios[i].port);
+ ret |= it8705f_write_enable(cfg->bcfg, superios[i].port);
break;
case 0x8686:
case 0x8716:

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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Ia48d4d4acd02550c72ee46bfe4042b3c75941da0
Gerrit-Change-Number: 73463
Gerrit-PatchSet: 1
Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org>
Gerrit-MessageType: newchange