Edward O'Callaghan has uploaded this change for review.
par_masters: Reshuffle to remove forward declarations
Dispense with all these forward declarations by way of
ordering. Just deal with all the par_masters in one go
to be over and done with.
BUG=none
BRANCH=none
TEST=builds
Change-Id: I88e89992380195fee7c9de7ec57502ab980ec5df
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M atahpt.c
M atapromise.c
M atavia.c
M gfxnvidia.c
M it8212.c
M nic3com.c
M nicintel.c
M nicnatsemi.c
M nicrealtek.c
M satamv.c
M satasii.c
11 files changed, 258 insertions(+), 293 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/73/54873/1
diff --git a/atahpt.c b/atahpt.c
index 620e894..327d74b 100644
--- a/atahpt.c
+++ b/atahpt.c
@@ -40,9 +40,19 @@
};
static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr);
+ chipaddr addr)
+{
+ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
+ OUTB(val, io_base_addr + BIOS_ROM_DATA);
+}
+
static uint8_t atahpt_chip_readb(const struct flashctx *flash,
- const chipaddr addr);
+ const chipaddr addr)
+{
+ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
+ return INB(io_base_addr + BIOS_ROM_DATA);
+}
+
static const struct par_master par_master_atahpt = {
.chip_readb = atahpt_chip_readb,
.chip_readw = fallback_chip_readw,
@@ -80,20 +90,6 @@
return 0;
}
-static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr)
-{
- OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
- OUTB(val, io_base_addr + BIOS_ROM_DATA);
-}
-
-static uint8_t atahpt_chip_readb(const struct flashctx *flash,
- const chipaddr addr)
-{
- OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
- return INB(io_base_addr + BIOS_ROM_DATA);
-}
-
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif
diff --git a/atapromise.c b/atapromise.c
index f32bdb4..4941a7c 100644
--- a/atapromise.c
+++ b/atapromise.c
@@ -53,20 +53,6 @@
{0},
};
-static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
-static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr);
-
-static const struct par_master par_master_atapromise = {
- .chip_readb = atapromise_chip_readb,
- .chip_readw = fallback_chip_readw,
- .chip_readl = fallback_chip_readl,
- .chip_readn = fallback_chip_readn,
- .chip_writeb = atapromise_chip_writeb,
- .chip_writew = fallback_chip_writew,
- .chip_writel = fallback_chip_writel,
- .chip_writen = fallback_chip_writen,
-};
-
void *atapromise_map(const char *descr, uintptr_t phys_addr, size_t len)
{
/* In case fallback_map ever returns something other than NULL. */
@@ -106,6 +92,32 @@
}
}
+static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
+{
+ uint32_t data;
+
+ atapromise_limit_chip(flash->chip);
+ data = (rom_base_addr + (addr & ADDR_MASK)) << 8 | val;
+ OUTL(data, io_base_addr + 0x14);
+}
+
+static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr)
+{
+ atapromise_limit_chip(flash->chip);
+ return pci_mmio_readb(atapromise_bar + (addr & ADDR_MASK));
+}
+
+static const struct par_master par_master_atapromise = {
+ .chip_readb = atapromise_chip_readb,
+ .chip_readw = fallback_chip_readw,
+ .chip_readl = fallback_chip_readl,
+ .chip_readn = fallback_chip_readn,
+ .chip_writeb = atapromise_chip_writeb,
+ .chip_writew = fallback_chip_writew,
+ .chip_writel = fallback_chip_writel,
+ .chip_writen = fallback_chip_writen,
+};
+
int atapromise_init(void)
{
struct pci_dev *dev = NULL;
@@ -150,21 +162,6 @@
return 0;
}
-static void atapromise_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
-{
- uint32_t data;
-
- atapromise_limit_chip(flash->chip);
- data = (rom_base_addr + (addr & ADDR_MASK)) << 8 | val;
- OUTL(data, io_base_addr + 0x14);
-}
-
-static uint8_t atapromise_chip_readb(const struct flashctx *flash, const chipaddr addr)
-{
- atapromise_limit_chip(flash->chip);
- return pci_mmio_readb(atapromise_bar + (addr & ADDR_MASK));
-}
-
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif
diff --git a/atavia.c b/atavia.c
index e04950a..8045e1b 100644
--- a/atavia.c
+++ b/atavia.c
@@ -54,19 +54,6 @@
{0},
};
-static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
-static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr);
-static const struct par_master lpc_master_atavia = {
- .chip_readb = atavia_chip_readb,
- .chip_readw = fallback_chip_readw,
- .chip_readl = fallback_chip_readl,
- .chip_readn = fallback_chip_readn,
- .chip_writeb = atavia_chip_writeb,
- .chip_writew = fallback_chip_writew,
- .chip_writel = fallback_chip_writel,
- .chip_writen = fallback_chip_writen,
-};
-
static void *atavia_offset = NULL;
static struct pci_dev *dev = NULL;
@@ -119,6 +106,43 @@
return (atavia_offset != 0) ? atavia_offset : (void *)phys_addr;
}
+static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, const chipaddr addr)
+{
+ msg_pspew("%s: 0x%02x to 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr);
+ pci_write_long(dev, BROM_ADDR, (addr & ~3));
+ pci_write_long(dev, BROM_DATA, val << BYTE_OFFSET(addr));
+ pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | BROM_WRITE | ENABLE_BYTE(addr));
+
+ if (!atavia_ready(dev)) {
+ msg_perr("not ready after write\n");
+ }
+}
+
+static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr)
+{
+ pci_write_long(dev, BROM_ADDR, (addr & ~3));
+ pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | ENABLE_BYTE(addr));
+
+ if (!atavia_ready(dev)) {
+ msg_perr("not ready after read\n");
+ }
+
+ uint8_t val = (pci_read_long(dev, BROM_DATA) >> BYTE_OFFSET(addr)) & 0xff;
+ msg_pspew("%s: 0x%02x from 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr);
+ return val;
+}
+
+static const struct par_master lpc_master_atavia = {
+ .chip_readb = atavia_chip_readb,
+ .chip_readw = fallback_chip_readw,
+ .chip_readl = fallback_chip_readl,
+ .chip_readn = fallback_chip_readn,
+ .chip_writeb = atavia_chip_writeb,
+ .chip_writew = fallback_chip_writew,
+ .chip_writel = fallback_chip_writel,
+ .chip_writen = fallback_chip_writen,
+};
+
int atavia_init(void)
{
char *arg = extract_programmer_param("offset");
@@ -164,29 +188,3 @@
return 0;
}
-
-static void atavia_chip_writeb(const struct flashctx *flash, uint8_t val, const chipaddr addr)
-{
- msg_pspew("%s: 0x%02x to 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr);
- pci_write_long(dev, BROM_ADDR, (addr & ~3));
- pci_write_long(dev, BROM_DATA, val << BYTE_OFFSET(addr));
- pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | BROM_WRITE | ENABLE_BYTE(addr));
-
- if (!atavia_ready(dev)) {
- msg_perr("not ready after write\n");
- }
-}
-
-static uint8_t atavia_chip_readb(const struct flashctx *flash, const chipaddr addr)
-{
- pci_write_long(dev, BROM_ADDR, (addr & ~3));
- pci_write_byte(dev, BROM_ACCESS, BROM_TRIGGER | ENABLE_BYTE(addr));
-
- if (!atavia_ready(dev)) {
- msg_perr("not ready after read\n");
- }
-
- uint8_t val = (pci_read_long(dev, BROM_DATA) >> BYTE_OFFSET(addr)) & 0xff;
- msg_pspew("%s: 0x%02x from 0x%*" PRIxPTR ".\n", __func__, val, PRIxPTR_WIDTH, addr);
- return val;
-}
diff --git a/gfxnvidia.c b/gfxnvidia.c
index fe6f982..6b1efcf 100644
--- a/gfxnvidia.c
+++ b/gfxnvidia.c
@@ -59,9 +59,17 @@
};
static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr);
+ chipaddr addr)
+{
+ pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
+}
+
static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
- const chipaddr addr);
+ const chipaddr addr)
+{
+ return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
+}
+
static const struct par_master par_master_gfxnvidia = {
.chip_readb = gfxnvidia_chip_readb,
.chip_readw = fallback_chip_readw,
@@ -107,15 +115,3 @@
return 0;
}
-
-static void gfxnvidia_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr)
-{
- pci_mmio_writeb(val, nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
-}
-
-static uint8_t gfxnvidia_chip_readb(const struct flashctx *flash,
- const chipaddr addr)
-{
- return pci_mmio_readb(nvidia_bar + (addr & GFXNVIDIA_MEMMAP_MASK));
-}
diff --git a/it8212.c b/it8212.c
index 2f2d43e..7c66a59 100644
--- a/it8212.c
+++ b/it8212.c
@@ -32,8 +32,16 @@
#define IT8212_MEMMAP_SIZE (128 * 1024)
#define IT8212_MEMMAP_MASK (IT8212_MEMMAP_SIZE - 1)
-static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
-static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr);
+static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
+{
+ pci_mmio_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK));
+}
+
+static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr)
+{
+ return pci_mmio_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK));
+}
+
static const struct par_master par_master_it8212 = {
.chip_readb = it8212_chip_readb,
.chip_readw = fallback_chip_readw,
@@ -70,13 +78,3 @@
register_par_master(&par_master_it8212, BUS_PARALLEL, NULL);
return 0;
}
-
-static void it8212_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
-{
- pci_mmio_writeb(val, it8212_bar + (addr & IT8212_MEMMAP_MASK));
-}
-
-static uint8_t it8212_chip_readb(const struct flashctx *flash, const chipaddr addr)
-{
- return pci_mmio_readb(it8212_bar + (addr & IT8212_MEMMAP_MASK));
-}
diff --git a/nic3com.c b/nic3com.c
index 6ff91e7..d60b03c 100644
--- a/nic3com.c
+++ b/nic3com.c
@@ -54,9 +54,19 @@
};
static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr);
+ chipaddr addr)
+{
+ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
+ OUTB(val, io_base_addr + BIOS_ROM_DATA);
+}
+
static uint8_t nic3com_chip_readb(const struct flashctx *flash,
- const chipaddr addr);
+ const chipaddr addr)
+{
+ OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
+ return INB(io_base_addr + BIOS_ROM_DATA);
+}
+
static const struct par_master par_master_nic3com = {
.chip_readb = nic3com_chip_readb,
.chip_readw = fallback_chip_readw,
@@ -125,20 +135,6 @@
return 0;
}
-static void nic3com_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr)
-{
- OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
- OUTB(val, io_base_addr + BIOS_ROM_DATA);
-}
-
-static uint8_t nic3com_chip_readb(const struct flashctx *flash,
- const chipaddr addr)
-{
- OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
- return INB(io_base_addr + BIOS_ROM_DATA);
-}
-
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif
diff --git a/nicintel.c b/nicintel.c
index afd2682..3d324da 100644
--- a/nicintel.c
+++ b/nicintel.c
@@ -41,9 +41,17 @@
#define CSR_FCR 0x0c
static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr);
+ chipaddr addr)
+{
+ pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
+}
+
static uint8_t nicintel_chip_readb(const struct flashctx *flash,
- const chipaddr addr);
+ const chipaddr addr)
+{
+ return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
+}
+
static const struct par_master par_master_nicintel = {
.chip_readb = nicintel_chip_readb,
.chip_readw = fallback_chip_readw,
@@ -103,15 +111,3 @@
return 0;
}
-
-static void nicintel_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr)
-{
- pci_mmio_writeb(val, nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
-}
-
-static uint8_t nicintel_chip_readb(const struct flashctx *flash,
- const chipaddr addr)
-{
- return pci_mmio_readb(nicintel_bar + (addr & NICINTEL_MEMMAP_MASK));
-}
diff --git a/nicnatsemi.c b/nicnatsemi.c
index 77b5440..56297fe 100644
--- a/nicnatsemi.c
+++ b/nicnatsemi.c
@@ -35,9 +35,35 @@
};
static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr);
+ chipaddr addr)
+{
+ OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR);
+ /*
+ * The datasheet requires 32 bit accesses to this register, but it seems
+ * that requirement might only apply if the register is memory mapped.
+ * Bits 8-31 of this register are apparently don't care, and if this
+ * register is I/O port mapped, 8 bit accesses to the lowest byte of the
+ * register seem to work fine. Due to that, we ignore the advice in the
+ * data sheet.
+ */
+ OUTB(val, io_base_addr + BOOT_ROM_DATA);
+}
+
static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
- const chipaddr addr);
+ const chipaddr addr)
+{
+ OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR);
+ /*
+ * The datasheet requires 32 bit accesses to this register, but it seems
+ * that requirement might only apply if the register is memory mapped.
+ * Bits 8-31 of this register are apparently don't care, and if this
+ * register is I/O port mapped, 8 bit accesses to the lowest byte of the
+ * register seem to work fine. Due to that, we ignore the advice in the
+ * data sheet.
+ */
+ return INB(io_base_addr + BOOT_ROM_DATA);
+}
+
static const struct par_master par_master_nicnatsemi = {
.chip_readb = nicnatsemi_chip_readb,
.chip_readw = fallback_chip_readw,
@@ -76,36 +102,6 @@
return 0;
}
-static void nicnatsemi_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr)
-{
- OUTL((uint32_t)addr & 0x0001FFFF, io_base_addr + BOOT_ROM_ADDR);
- /*
- * The datasheet requires 32 bit accesses to this register, but it seems
- * that requirement might only apply if the register is memory mapped.
- * Bits 8-31 of this register are apparently don't care, and if this
- * register is I/O port mapped, 8 bit accesses to the lowest byte of the
- * register seem to work fine. Due to that, we ignore the advice in the
- * data sheet.
- */
- OUTB(val, io_base_addr + BOOT_ROM_DATA);
-}
-
-static uint8_t nicnatsemi_chip_readb(const struct flashctx *flash,
- const chipaddr addr)
-{
- OUTL(((uint32_t)addr & 0x0001FFFF), io_base_addr + BOOT_ROM_ADDR);
- /*
- * The datasheet requires 32 bit accesses to this register, but it seems
- * that requirement might only apply if the register is memory mapped.
- * Bits 8-31 of this register are apparently don't care, and if this
- * register is I/O port mapped, 8 bit accesses to the lowest byte of the
- * register seem to work fine. Due to that, we ignore the advice in the
- * data sheet.
- */
- return INB(io_base_addr + BOOT_ROM_DATA);
-}
-
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif
diff --git a/nicrealtek.c b/nicrealtek.c
index 2208179..788c088 100644
--- a/nicrealtek.c
+++ b/nicrealtek.c
@@ -35,8 +35,44 @@
{0},
};
-static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
-static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr);
+static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
+{
+ /* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
+ * enable software access.
+ */
+ OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
+ io_base_addr + bios_rom_addr);
+ /* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
+ * enable software access.
+ */
+ OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
+ io_base_addr + bios_rom_addr);
+}
+
+static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
+{
+ uint8_t val;
+
+ /* FIXME: Can we skip reading the old data and simply use 0? */
+ /* Read old data. */
+ val = INB(io_base_addr + bios_rom_data);
+ /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
+ * enable software access.
+ */
+ OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
+ io_base_addr + bios_rom_addr);
+
+ /* Read new data. */
+ val = INB(io_base_addr + bios_rom_data);
+ /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
+ * enable software access.
+ */
+ OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
+ io_base_addr + bios_rom_addr);
+
+ return val;
+}
+
static const struct par_master par_master_nicrealtek = {
.chip_readb = nicrealtek_chip_readb,
.chip_readw = fallback_chip_readw,
@@ -91,44 +127,6 @@
return 0;
}
-static void nicrealtek_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
-{
- /* Output addr and data, set WE to 0, set OE to 1, set CS to 0,
- * enable software access.
- */
- OUTL(((uint32_t)addr & 0x01FFFF) | 0x0A0000 | (val << 24),
- io_base_addr + bios_rom_addr);
- /* Output addr and data, set WE to 1, set OE to 1, set CS to 1,
- * enable software access.
- */
- OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
- io_base_addr + bios_rom_addr);
-}
-
-static uint8_t nicrealtek_chip_readb(const struct flashctx *flash, const chipaddr addr)
-{
- uint8_t val;
-
- /* FIXME: Can we skip reading the old data and simply use 0? */
- /* Read old data. */
- val = INB(io_base_addr + bios_rom_data);
- /* Output new addr and old data, set WE to 1, set OE to 0, set CS to 0,
- * enable software access.
- */
- OUTL(((uint32_t)addr & 0x01FFFF) | 0x060000 | (val << 24),
- io_base_addr + bios_rom_addr);
-
- /* Read new data. */
- val = INB(io_base_addr + bios_rom_data);
- /* Output addr and new data, set WE to 1, set OE to 1, set CS to 1,
- * enable software access.
- */
- OUTL(((uint32_t)addr & 0x01FFFF) | 0x1E0000 | (val << 24),
- io_base_addr + bios_rom_addr);
-
- return val;
-}
-
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif
diff --git a/satamv.c b/satamv.c
index 2640b78..30b7c34 100644
--- a/satamv.c
+++ b/satamv.c
@@ -38,10 +38,41 @@
#define PCI_BAR2_CONTROL 0x00c08
#define GPIO_PORT_CONTROL 0x104f0
+/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
+ * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).
+ * This code only supports indirect accesses for now.
+ */
+
+/* Indirect access to via the I/O BAR1. */
+static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)
+{
+ /* 0x80000000 selects BAR2 for remapping. */
+ OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
+ OUTB(val, mv_iobar + 0x80 + (addr & 0x3));
+}
+
+/* Indirect access to via the I/O BAR1. */
+static uint8_t satamv_indirect_chip_readb(const chipaddr addr)
+{
+ /* 0x80000000 selects BAR2 for remapping. */
+ OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
+ return INB(mv_iobar + 0x80 + (addr & 0x3));
+}
+
+/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr);
+ chipaddr addr)
+{
+ satamv_indirect_chip_writeb(val, addr);
+}
+
+/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
static uint8_t satamv_chip_readb(const struct flashctx *flash,
- const chipaddr addr);
+ const chipaddr addr)
+{
+ return satamv_indirect_chip_readb(addr);
+}
+
static const struct par_master par_master_satamv = {
.chip_readb = satamv_chip_readb,
.chip_readw = fallback_chip_readw,
@@ -153,41 +184,6 @@
return 0;
}
-/* BAR2 (MEM) can map NVRAM and flash. We set it to flash in the init function.
- * If BAR2 is disabled, it still can be accessed indirectly via BAR1 (I/O).
- * This code only supports indirect accesses for now.
- */
-
-/* Indirect access to via the I/O BAR1. */
-static void satamv_indirect_chip_writeb(uint8_t val, chipaddr addr)
-{
- /* 0x80000000 selects BAR2 for remapping. */
- OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
- OUTB(val, mv_iobar + 0x80 + (addr & 0x3));
-}
-
-/* Indirect access to via the I/O BAR1. */
-static uint8_t satamv_indirect_chip_readb(const chipaddr addr)
-{
- /* 0x80000000 selects BAR2 for remapping. */
- OUTL(((uint32_t)addr | 0x80000000) & 0xfffffffc, mv_iobar);
- return INB(mv_iobar + 0x80 + (addr & 0x3));
-}
-
-/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
-static void satamv_chip_writeb(const struct flashctx *flash, uint8_t val,
- chipaddr addr)
-{
- satamv_indirect_chip_writeb(val, addr);
-}
-
-/* FIXME: Prefer direct access to BAR2 if BAR2 is active. */
-static uint8_t satamv_chip_readb(const struct flashctx *flash,
- const chipaddr addr)
-{
- return satamv_indirect_chip_readb(addr);
-}
-
#else
#error PCI port I/O access is not supported on this architecture yet.
#endif
diff --git a/satasii.c b/satasii.c
index c9dfdad..0d22650 100644
--- a/satasii.c
+++ b/satasii.c
@@ -37,19 +37,6 @@
{0},
};
-static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr);
-static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr);
-static const struct par_master par_master_satasii = {
- .chip_readb = satasii_chip_readb,
- .chip_readw = fallback_chip_readw,
- .chip_readl = fallback_chip_readl,
- .chip_readn = fallback_chip_readn,
- .chip_writeb = satasii_chip_writeb,
- .chip_writew = fallback_chip_writew,
- .chip_writel = fallback_chip_writel,
- .chip_writen = fallback_chip_writen,
-};
-
static uint32_t satasii_wait_done(void)
{
uint32_t ctrl_reg;
@@ -64,6 +51,48 @@
return ctrl_reg;
}
+static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
+{
+ uint32_t data_reg;
+ uint32_t ctrl_reg = satasii_wait_done();
+
+ /* Mask out unused/reserved bits, set writes and start transaction. */
+ ctrl_reg &= 0xfcf80000;
+ ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);
+
+ data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val;
+ pci_mmio_writel(data_reg, (sii_bar + 4));
+ pci_mmio_writel(ctrl_reg, sii_bar);
+
+ satasii_wait_done();
+}
+
+static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr)
+{
+ uint32_t ctrl_reg = satasii_wait_done();
+
+ /* Mask out unused/reserved bits, set reads and start transaction. */
+ ctrl_reg &= 0xfcf80000;
+ ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);
+
+ pci_mmio_writel(ctrl_reg, sii_bar);
+
+ satasii_wait_done();
+
+ return (pci_mmio_readl(sii_bar + 4)) & 0xff;
+}
+
+static const struct par_master par_master_satasii = {
+ .chip_readb = satasii_chip_readb,
+ .chip_readw = fallback_chip_readw,
+ .chip_readl = fallback_chip_readl,
+ .chip_readn = fallback_chip_readn,
+ .chip_writeb = satasii_chip_writeb,
+ .chip_writew = fallback_chip_writew,
+ .chip_writel = fallback_chip_writel,
+ .chip_writen = fallback_chip_writen,
+};
+
int satasii_init(void)
{
struct pci_dev *dev = NULL;
@@ -104,34 +133,3 @@
return 0;
}
-
-static void satasii_chip_writeb(const struct flashctx *flash, uint8_t val, chipaddr addr)
-{
- uint32_t data_reg;
- uint32_t ctrl_reg = satasii_wait_done();
-
- /* Mask out unused/reserved bits, set writes and start transaction. */
- ctrl_reg &= 0xfcf80000;
- ctrl_reg |= (1 << 25) | (0 << 24) | ((uint32_t) addr & 0x7ffff);
-
- data_reg = (pci_mmio_readl((sii_bar + 4)) & ~0xff) | val;
- pci_mmio_writel(data_reg, (sii_bar + 4));
- pci_mmio_writel(ctrl_reg, sii_bar);
-
- satasii_wait_done();
-}
-
-static uint8_t satasii_chip_readb(const struct flashctx *flash, const chipaddr addr)
-{
- uint32_t ctrl_reg = satasii_wait_done();
-
- /* Mask out unused/reserved bits, set reads and start transaction. */
- ctrl_reg &= 0xfcf80000;
- ctrl_reg |= (1 << 25) | (1 << 24) | ((uint32_t) addr & 0x7ffff);
-
- pci_mmio_writel(ctrl_reg, sii_bar);
-
- satasii_wait_done();
-
- return (pci_mmio_readl(sii_bar + 4)) & 0xff;
-}
To view, visit change 54873. To unsubscribe, or for help writing mail filters, visit settings.