Mayur Panchal would like David Hendricks to review this change.
use JEDEC_SE as the default sector erase opcode for ICH southbridge
Note: We should definitely look into on-the-fly opcode reprogramming
as the comment in ich_spi_send_multicommand() suggests.
Review URL: http://codereview.chromium.org/3239001
Change-Id: I379549e8fa966e75e3d8b7932700df62cf50df64
Signed-off-by: Mayur Panchal <panchalm@google.com>
---
M ichspi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/89/34689/1
diff --git a/ichspi.c b/ichspi.c
index 8b8f0f6..fc61262 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -324,7 +324,7 @@
{
{JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
{JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
- {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
+ {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
{JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
{JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
{JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
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