Edward O'Callaghan uploaded patch set #2 to this change.

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realtek_mst_i2c_spi.c: Fix _spi_send_command cb for erasures

Before issuing SPI opcodes into 0x61 the top three BITS of
0x60 need to be carefully crafted. Correctly craft these
in the case of SPI erasures and document this registers
expectations. Clean up remaining debug comments while we
are here.

BUG=b:152558985,b:148745673
BRANCH=none
TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E &&
flashrom -p realtek_mst_i2c_spi:bus=8 -r foo &&
hexdump -C foo

Change-Id: Ib11ba8f63b11a1c5ebaa68deb7971648de8c2ecd
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M realtek_mst_i2c_spi.c
1 file changed, 40 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/41079/2

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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: Ib11ba8f63b11a1c5ebaa68deb7971648de8c2ecd
Gerrit-Change-Number: 41079
Gerrit-PatchSet: 2
Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Edward Hill <ecgh@chromium.org>
Gerrit-Reviewer: Sam McNally <sammc@google.com>
Gerrit-Reviewer: Shiyu Sun <sshiyu@google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-MessageType: newpatchset