Edward O'Callaghan has uploaded this change for review.
flashrom: Rename 'max_rom_decode' to 'g_max_rom_decode'
The next step appears that g_max_rom_decode is a natural
fit into the internal.c driver. Apart from 'wbsio_spi.c'
not sure what to do there???
Change-Id: I22785fb196c15dea0500b650bfbc4151983d9d0e
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M cli_classic.c
M flashrom.c
M include/programmer.h
M internal.c
M parallel.c
M wbsio_spi.c
6 files changed, 25 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/78/68678/1
diff --git a/cli_classic.c b/cli_classic.c
index ad485a2..795335c 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -567,7 +567,7 @@
*/
static bool max_rom_decode_limitexceeded(const struct flashctx *flash, bool force)
{
- const unsigned int limitexceeded = count_max_decode_exceedings(flash, &max_rom_decode);
+ const unsigned int limitexceeded = count_max_decode_exceedings(flash, &g_max_rom_decode);
if (limitexceeded > 0 && !force) {
enum chipbustype commonbuses = flash->mst->buses_supported & flash->chip->bustype;
diff --git a/flashrom.c b/flashrom.c
index 0f982c9..531cfb7 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -43,7 +43,7 @@
* Programmers supporting multiple buses can have differing size limits on
* each bus. Store the limits for each bus in a common struct.
*/
-struct decode_sizes max_rom_decode;
+struct decode_sizes g_max_rom_decode;
/* If nonzero, used as the start address of bottom-aligned flash. */
unsigned long flashbase;
@@ -136,7 +136,7 @@
programmer = prog;
/* Initialize all programmer specific data. */
/* Default to unlimited decode sizes. */
- max_rom_decode = (const struct decode_sizes) {
+ g_max_rom_decode = (const struct decode_sizes) {
.parallel = 0xffffffff,
.lpc = 0xffffffff,
.fwh = 0xffffffff,
diff --git a/include/programmer.h b/include/programmer.h
index e8f5ccc..22a50c7 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -285,7 +285,7 @@
/* flashrom.c */
// FIXME: These need to be local, not global
-extern struct decode_sizes max_rom_decode;
+extern struct decode_sizes g_max_rom_decode;
extern bool programmer_may_write;
extern unsigned long flashbase;
char *extract_programmer_param_str(const struct programmer_cfg *cfg, const char *param_name);
diff --git a/internal.c b/internal.c
index 7cd3f22..7868a8d 100644
--- a/internal.c
+++ b/internal.c
@@ -285,7 +285,7 @@
/* try to enable it. Failure IS an option, since not all motherboards
* really need this to be done, etc., etc.
*/
- ret = chipset_flash_enable(cfg, &max_rom_decode);
+ ret = chipset_flash_enable(cfg, &g_max_rom_decode);
if (ret == -2) {
msg_perr("WARNING: No chipset found. Flash detection "
"will most likely fail.\n");
@@ -296,9 +296,9 @@
#if defined(__i386__) || defined(__x86_64__)
/* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and
* parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */
- init_superio_ite(cfg, &max_rom_decode);
+ init_superio_ite(cfg, &g_max_rom_decode);
- if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model, &max_rom_decode)) {
+ if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model, &g_max_rom_decode)) {
msg_perr("Aborting to be safe.\n");
ret = 1;
goto internal_init_exit;
@@ -306,7 +306,7 @@
#endif
if (internal_buses_supported & BUS_NONSPI)
- register_par_master(&par_master_internal, internal_buses_supported, NULL, max_rom_decode.parallel);
+ register_par_master(&par_master_internal, internal_buses_supported, NULL, g_max_rom_decode.parallel);
/* Report if a non-whitelisted laptop is detected that likely uses a legacy bus. */
if (is_laptop && !laptop_ok) {
diff --git a/parallel.c b/parallel.c
index 67e70f6..72ef657 100644
--- a/parallel.c
+++ b/parallel.c
@@ -97,9 +97,9 @@
}
if (max_decode_size)
- max_rom_decode.parallel = max_decode_size;
+ g_max_rom_decode.parallel = max_decode_size;
else
- max_rom_decode.parallel = 0xffffffff;
+ g_max_rom_decode.parallel = 0xffffffff;
rmst.buses_supported = buses;
rmst.par = *mst;
diff --git a/wbsio_spi.c b/wbsio_spi.c
index 1aa8729..379d6f8 100644
--- a/wbsio_spi.c
+++ b/wbsio_spi.c
@@ -208,7 +208,7 @@
msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is "
"1024 kB!\n", __func__);
- max_rom_decode.spi = 1024 * 1024;
+ g_max_rom_decode.spi = 1024 * 1024;
struct wbsio_spi_data *data = calloc(1, sizeof(*data));
if (!data) {
To view, visit change 68678. To unsubscribe, or for help writing mail filters, visit settings.