Jonathon Hall has uploaded this change for review.
ichspi: Do not mmap for hwseq
Flash chips >16 MB can't be directly mapped into memory, this usually
results in a failure since the attempted mapping would overlap with PCI
devices. The mapping isn't needed for these methods.
This change is likely also correct for ICH swseq and possibly others,
these would need to be tested.
Test: Probe and read firmware on 400-series PCH with 16 MB and 32 MB
SPI flash
Change-Id: Ic7761327b4072dcb9917000db9eaacc9404e6823
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
---
M ichspi.c
1 file changed, 22 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/96/67696/1
diff --git a/ichspi.c b/ichspi.c
index 77822fd..5dd5c9c 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -2207,7 +2207,7 @@
register_opaque_master(&opaque_master_ich_hwseq, NULL, &g_hwseq_data);
} else {
- register_spi_master(&spi_master_ich9, NULL, NULL);
+ register_spi_master(&spi_master_ich9, &mapper_phys, NULL);
}
return 0;
@@ -2252,7 +2252,7 @@
/* Not sure if it speaks all these bus protocols. */
internal_buses_supported &= BUS_LPC | BUS_FWH;
ich_generation = CHIPSET_ICH7;
- register_spi_master(&spi_master_via, NULL, NULL);
+ register_spi_master(&spi_master_via, &mapper_phys, NULL);
msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
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