Attention is currently required from: Edward O'Callaghan.
Edward O'Callaghan uploaded patch set #5 to this change.
cbtable.c: don't assume high addresses can fully map 1 MiB
Forward port the downstream `commit b17e9e41838`.
When using a forwarding table entry for finding the coreboot table
don't assume one has access to a full 1 MiB where the forwarding
table entry points to. The reason is that the 1 MiB may cover address
regions that have differing cacheability type. As such the kernel will
complain and the mapping will fail. Instead, check the header first then
map in the bytes that it indicates after sanity validation. That way
there is no attempt at requesting an invalid mapping that spans different
memory cacheability attributes.
V.2: Incorperate Nico's and Angels comments from upstream.
TEST=Can successfully run 'flashrom -p host --wp-status' on kahlee
without generating PAT errors.
Original-Signed-off-by: Aaron Durbin <firstname.lastname@example.org>
Original-Reviewed-by: Martin Roth <email@example.com>
Original-Reviewed-by: Justin TerAvest <firstname.lastname@example.org>
Signed-off-by: Edward O'Callaghan <email@example.com>
1 file changed, 57 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/40/37240/5
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