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2 comments:

• File nicintel_eeprom.c:

  • Patch Set #1, Line 103: {PCI_VENDOR_ID_INTEL, 0x1522, NT, "Intel", "I350 Gigabit Network Connection External SGMII PHY"},

    0x1522? Should be 0x1524?

    yes good catch

  • Patch Set #1, Line 477: uintptr_t io_base_addr = pcidev_readbar(dev, PCI_BASE_ADDRESS_0);

    This change is probably needed because most PCI devices on x86_64 use 32-bit BARs

    it is needed as my platform is arm64 and the BAR0 has an address above the 32 bit boundary even if the pci device might not see it that way.
    Maybe a fixed size 64 bit would be more appropriate ?

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