Attention is currently required from: Hsuan Ting Chen.

Hsuan-ting Chen would like Hsuan Ting Chen to review this change.

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how_to_add_new_chip: Add a section for feature bits and WRSR handling

Feature bits are too complicated to understand if we only read the
codes/datasheets. Add a new section in how_to_add_new_chip to add more
details about each feature bits.

Add the detailed explanation for WRSR handling first. If this new
section looks good, I'll try to add some more sections in further
commits.

BUG=b:345154585
TEST=meson compile -C builddir and view the doc.

Change-Id: I34c20933a375380c8702f79ac637595cd3466000
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
---
M doc/contrib_howtos/how_to_add_new_chip.rst
1 file changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/08/82908/1

diff --git a/doc/contrib_howtos/how_to_add_new_chip.rst b/doc/contrib_howtos/how_to_add_new_chip.rst
index b046ac3..ed25d29 100644
--- a/doc/contrib_howtos/how_to_add_new_chip.rst
+++ b/doc/contrib_howtos/how_to_add_new_chip.rst
@@ -102,6 +102,31 @@
   in ``include/flash.h``. Without any tests it should be set to ``TEST_UNTESTED``.
   See also another doc :doc:`how_to_mark_chip_tested`.
 
+Feature Bits
+-------------
+
+The ``.feature_bits`` field in a chip definition encodes various features using a bitmask.
+Here are some of the selected feature bits that need to be highlighted:
+
+Write-Status-Register (WRSR) Handling
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+``FEATURE_WRSR_EWSR``, ``FEATURE_WRSR_WREN``, and ``FEATURE_WRSR_EITHER``. These bits used for **SPI only**.
+
+The Write Status Register (WRSR) is used to configure various settings within the flash chip, including write protection and
+other features. The way WRSR is accessed varies between SPI flash chips, leading to the need for these feature bits.
+
+* ``FEATURE_WRSR_EWSR``:
+  This indicates that we need an **Enable-Write-Status-Register** (EWSR) instruction which opens the status register for the
+  immediately-followed next WRSR instruction. Usually, the opcode is **0x50**.
+
+* ``FEATURE_WRSR_WREN``:
+  This indicates that we need an **Write-Enable** (WREN) instruction to set the Write Enable Latch (WEL) bit. The WEL bit
+  must be set priort to every WRSR command. Usually, the opcode is **0x06**.
+
+* ``FEATURE_WRSR_EITHER``:
+  This indicates that either EWSR or WREN is supported in this chip.
+
 Operations
 ==========
 

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