Attention is currently required from: Bora Guvendik, Anil Kumar K, Paul Menzel, Edward O'Callaghan, Angel Pons, Nikolai Artemiev, Anastasia Klimchuk.

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2 comments:

• Patchset:

  • Patch Set #7:

    Anil, thanks for your patch. It's nice to see that Intel gets involved
    with flashrom. Before adding IDs for new chipset generations, we have
    to check if the selected code paths are compatible, as we want to keep
    the code base as consistent as possible. Maybe it's best to add one
    generation at a time in separate commits. Tiger Lake already has such
    a commit on Gerrit btw. (CB:55578). Ice Lake, Jasper Lake and Alder Lake
    still need to be looked into, I guess.

    Some hints how to add new Intel chipset generations:

    • Generally one needs the EDS and the SPI Programming Guide.
    • The function pointer in the PCI device table indirectly sets the generation (one of `enum ich_chipset`). For instance, CHIPSET_100_SERIES_SUNRISE_POINT. Not every new generation needs its own enum entry, but one should have a look if all code paths taken for a given entry match the new hardware. If there is no 100% compatible enum entry, then it's time to add a new one.
    • We also try to keep track of changes in the Flash Descriptor. And as Intel didn't give it a version number or anything like that, we try to detect the version by its contents (cf. guess_ich_chipset_from_content()). This is sometimes very fiddly, let us know if you need help with it.

    tl;dr
    Follow all the if and switch/case statements for `enum ich_chipset` to see
    what matches the new hardware and descriptor.

• File chipset_enable.c:

  • Patch Set #7, Line 2018:

    {0x8086, 0xa224, B_FS,   OK,  "Intel", "Lewisburg",			enable_flash_pch100},
    	{0x8086, 0x9da4, B_FS,   OK,  "Intel", "Cannonlake",			enable_flash_pch100},
    	{0x8086, 0x34a4, B_FS,   OK,  "Intel", "Icelake",			enable_flash_pch100},
    	{0x8086, 0x4da4, B_FS,   OK,  "Intel", "Jasperlake",			enable_flash_pch100},
    	{0x8086, 0xa0a4, B_FS,   OK,  "Intel", "Tigerlake",			enable_flash_pch100},
    	{0x8086, 0x7aa4, B_FS,   OK,  "Intel", "Alderlake-S",			enable_flash_pch100},
    	{0x8086, 0x51a4, B_FS,   OK,  "Intel", "Alderlake-P / M",	        enable_flash_pch100},
    

    flashrom uses LPC/eSPI PCI IDs instead of SPI PCI IDs. The SPI PCI device is not always visible, and didn't exist before Sunrise Point.

    If intel could provide documentation on what chipsets the SPI device is
    guaranteed to be visible, that would be nice. Then we could save us adding
    all the LPC/eSPI IDs for these chipsets. I just checked a Tiger Lake EDS
    and the bit to hide the device is reserved now.

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