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Patch set 4:Code-Review +1

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• Patchset:

  • Patch Set #2:

    > > > > > This leaves some questions. Is something broken wrt. arbitration? How does […]

    If there is a Hardware Sequencing Cycle In Progress and an attempt is made to program any of the control, address, or data register the cycle is blocked and the FCERR bit is set. So a check is required in flashrom on H_SCIP, so that multiple instances (on same master) do not cancel each other's requests.

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