Edward O'Callaghan has uploaded this change for review.

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flashrom.8.tmpl: Add raiden_debug_spi doc entry

BUG=b:224358254
TEST=`man ./flashrom.8.tmpl`.

Change-Id: I186920006bdfcc7a9f89542f84b452dfc72b18e4
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M flashrom.8.tmpl
1 file changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/68/62768/1
diff --git a/flashrom.8.tmpl b/flashrom.8.tmpl
index fe2d9d6..d72ea01 100644
--- a/flashrom.8.tmpl
+++ b/flashrom.8.tmpl
@@ -358,6 +358,8 @@
.sp
.BR "* rayer_spi" " (for SPI flash ROMs attached to a parallel port by one of various cable types)"
.sp
+.BR "* raiden_debug_spi" " (for SPI flash ROMs attached to a ChromiumOS servo debug board)"
+.sp
.BR "* pony_spi" " (for SPI flash ROMs attached to a SI-Prog serial port "
bitbanging adapter)
.sp
@@ -1124,6 +1126,39 @@
The schematic of the Xilinx DLC 5 was published in
.URLB "http://www.xilinx.com/support/documentation/user_guides/xtp029.pdf" "a Xilinx user guide" .
.SS
+.BR "raiden_debug_spi " programmer
+.IP
+The target of the SPI flashing mux must be specified with the
+.B target
+parameter with the
+.sp
+.B " flashrom \-p raiden_debug_spi:target=[ec|ap]"
+.sp
+syntax where
+.B target
+is either the "EC" or "AP" SPI flash to program.
+.sp
+The default is to use the first available servo. You can use the optional
+.B serial
+parameter to specify the servo serial to use
+.sp
+.B " flashrom \-p raiden_debug_spi:serial=XXX"
+.sp
+syntax.
+.sp
+Allow for power to settle on the AP and EC flash devices using a default of 1-3ms.
+You can use the optional
+.B custom_rst
+parameter to specify the reset to use up to 10ms for from power on to the first write with
+.sp
+.B " flashrom \-p raiden_debug_spi:custom_rst=(true,false)"
+.sp
+syntax.
+.sp
+More information about the ChromiumOS servo hardware is available at
+.nh
+.URLB "https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/HEAD/docs/servo_v4.md" "servo website" .
+.SS
.BR "pony_spi " programmer
.IP
The serial port (like /dev/ttyS0, /dev/ttyUSB0 on Linux or COM3 on windows) is
@@ -1453,6 +1488,9 @@
.B rayer_spi
needs raw I/O port access.
.sp
+.B raiden_debug_spi
+need access to the respective USB device via libusb API version 1.0.
+.sp
.BR satasii ", " nicintel ", " nicintel_eeprom " and " nicintel_spi
need PCI configuration space read access and raw memory access.
.sp

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Gerrit-Project: flashrom
Gerrit-Branch: master
Gerrit-Change-Id: I186920006bdfcc7a9f89542f84b452dfc72b18e4
Gerrit-Change-Number: 62768
Gerrit-PatchSet: 1
Gerrit-Owner: Edward O'Callaghan <quasisec@chromium.org>
Gerrit-MessageType: newchange