Edward O'Callaghan has uploaded this change for review.
wbsio_spi.c: Drop unmaintained driver path
The 'Intel D201GLY' board is extremely old and the specialised
superio path it uses is highly bespoke to it. This causes a undue
maintenance burden to core flashrom data structures in how the
spi driver entry-point is dispatched via a board_enable hook.
Therefore in the cost-benefit just deprecate it to allow the
overall flashrom project to progress.
Change-Id: I25c4d02126fcf183662dec73a800cac3988a1773
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M Makefile
M board_enable.c
M include/programmer.h
M meson.build
D wbsio_spi.c
5 files changed, 19 insertions(+), 227 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/28/72828/1
diff --git a/Makefile b/Makefile
index 2ebd370..3e8b1f5 100644
--- a/Makefile
+++ b/Makefile
@@ -584,7 +584,7 @@
ifeq ($(CONFIG_INTERNAL) $(CONFIG_INTERNAL_X86), yes yes)
FEATURE_FLAGS += -D'CONFIG_INTERNAL=1'
PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o \
- internal.o it87spi.o sb600spi.o superio.o amd_imc.o wbsio_spi.o mcp6x_spi.o \
+ internal.o it87spi.o sb600spi.o superio.o amd_imc.o mcp6x_spi.o \
ichspi.o dmi.o known_boards.o
ACTIVE_PROGRAMMERS += internal
endif
diff --git a/board_enable.c b/board_enable.c
index d35b151..6032529 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -2467,7 +2467,6 @@
{0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
{0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
{0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},
- {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
{0x8086, 0x27b8, 0x8086, 0xd606, 0x8086, 0x2770, 0x8086, 0xd606, "^D945GCNL$", NULL, NULL, P2, "Intel", "D945GCNL", 0, OK, p2_not_a_laptop},
{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
{0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
diff --git a/include/programmer.h b/include/programmer.h
index db32b2c..1ea53cd 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -391,9 +391,6 @@
/* sb600spi.c */
int sb600_probe_spi(const struct programmer_cfg *cfg, struct pci_dev *dev);
-
-/* wbsio_spi.c */
-int wbsio_check_for_spi(void);
#endif
/* opaque.c */
diff --git a/meson.build b/meson.build
index 57ac438..2e92fa5 100644
--- a/meson.build
+++ b/meson.build
@@ -249,7 +249,6 @@
'sb600spi.c',
'superio.c',
'amd_imc.c',
- 'wbsio_spi.c',
'mcp6x_spi.c',
'ichspi.c',
'dmi.c',
diff --git a/wbsio_spi.c b/wbsio_spi.c
deleted file mode 100644
index d635a09..0000000
--- a/wbsio_spi.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * This file is part of the flashrom project.
- *
- * Copyright (C) 2008 Peter Stuge <peter@stuge.se>
- * Copyright (C) 2009,2010 Carl-Daniel Hailfinger
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdlib.h>
-
-#include "flash.h"
-#include "chipdrivers.h"
-#include "programmer.h"
-#include "hwaccess_physmap.h"
-#include "hwaccess_x86_io.h"
-#include "spi.h"
-
-#define WBSIO_PORT1 0x2e
-#define WBSIO_PORT2 0x4e
-
-struct wbsio_spi_data {
- uint16_t spibase;
-};
-
-static uint16_t wbsio_get_spibase(uint16_t port)
-{
- uint8_t id;
- uint16_t flashport = 0;
-
- w836xx_ext_enter(port);
- id = sio_read(port, 0x20);
- if (id != 0xa0) {
- msg_perr("\nW83627 not found at 0x%x, id=0x%02x want=0xa0.\n", port, id);
- goto done;
- }
-
- if (0 == (sio_read(port, 0x24) & 2)) {
- msg_perr("\nW83627 found at 0x%x, but SPI pins are not enabled. (CR[0x24] bit 1=0)\n", port);
- goto done;
- }
-
- sio_write(port, 0x07, 0x06);
- if (0 == (sio_read(port, 0x30) & 1)) {
- msg_perr("\nW83627 found at 0x%x, but SPI is not enabled. (LDN6[0x30] bit 0=0)\n", port);
- goto done;
- }
-
- flashport = (sio_read(port, 0x62) << 8) | sio_read(port, 0x63);
-
-done:
- w836xx_ext_leave(port);
- return flashport;
-}
-
-/* W83627DHG has 11 command modes:
- * 1=1 command only
- * 2=1 command+1 data write
- * 3=1 command+2 data read
- * 4=1 command+3 address
- * 5=1 command+3 address+1 data write
- * 6=1 command+3 address+4 data write
- * 7=1 command+3 address+1 dummy address inserted by wbsio+4 data read
- * 8=1 command+3 address+1 data read
- * 9=1 command+3 address+2 data read
- * a=1 command+3 address+3 data read
- * b=1 command+3 address+4 data read
- *
- * mode[7:4] holds the command mode
- * mode[3:0] holds SPI address bits [19:16]
- *
- * The Winbond SPI master only supports 20 bit addresses on the SPI bus. :\
- * Would one more byte of RAM in the chip (to get all 24 bits) really make
- * such a big difference?
- */
-static int wbsio_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
- unsigned int readcnt,
- const unsigned char *writearr,
- unsigned char *readarr)
-{
- unsigned int i;
- uint8_t mode = 0;
-
- msg_pspew("%s:", __func__);
-
- const struct wbsio_spi_data *data =
- (const struct wbsio_spi_data *)flash->mst->spi.data;
-
- if (1 == writecnt && 0 == readcnt) {
- mode = 0x10;
- } else if (2 == writecnt && 0 == readcnt) {
- OUTB(writearr[1], data->spibase + 4);
- msg_pspew(" data=0x%02x", writearr[1]);
- mode = 0x20;
- } else if (1 == writecnt && 2 == readcnt) {
- mode = 0x30;
- } else if (4 == writecnt && 0 == readcnt) {
- msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
- for (i = 2; i < writecnt; i++) {
- OUTB(writearr[i], data->spibase + i);
- msg_pspew("%02x", writearr[i]);
- }
- mode = 0x40 | (writearr[1] & 0x0f);
- } else if (5 == writecnt && 0 == readcnt) {
- msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
- for (i = 2; i < 4; i++) {
- OUTB(writearr[i], data->spibase + i);
- msg_pspew("%02x", writearr[i]);
- }
- OUTB(writearr[i], data->spibase + i);
- msg_pspew(" data=0x%02x", writearr[i]);
- mode = 0x50 | (writearr[1] & 0x0f);
- } else if (8 == writecnt && 0 == readcnt) {
- msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
- for (i = 2; i < 4; i++) {
- OUTB(writearr[i], data->spibase + i);
- msg_pspew("%02x", writearr[i]);
- }
- msg_pspew(" data=0x");
- for (; i < writecnt; i++) {
- OUTB(writearr[i], data->spibase + i);
- msg_pspew("%02x", writearr[i]);
- }
- mode = 0x60 | (writearr[1] & 0x0f);
- } else if (5 == writecnt && 4 == readcnt) {
- /* XXX: TODO not supported by flashrom infrastructure!
- * This mode, 7, discards the fifth byte in writecnt,
- * but since we can not express that in flashrom, fail
- * the operation for now.
- */
- ;
- } else if (4 == writecnt && readcnt >= 1 && readcnt <= 4) {
- msg_pspew(" addr=0x%02x", (writearr[1] & 0x0f));
- for (i = 2; i < writecnt; i++) {
- OUTB(writearr[i], data->spibase + i);
- msg_pspew("%02x", writearr[i]);
- }
- mode = ((7 + readcnt) << 4) | (writearr[1] & 0x0f);
- }
- msg_pspew(" cmd=%02x mode=%02x\n", writearr[0], mode);
-
- if (!mode) {
- msg_perr("%s: unsupported command type wr=%d rd=%d\n",
- __func__, writecnt, readcnt);
- /* Command type refers to the number of bytes read/written. */
- return SPI_INVALID_LENGTH;
- }
-
- OUTB(writearr[0], data->spibase);
- OUTB(mode, data->spibase + 1);
- default_delay(10);
-
- if (!readcnt)
- return 0;
-
- msg_pspew("%s: returning data =", __func__);
- for (i = 0; i < readcnt; i++) {
- readarr[i] = INB(data->spibase + 4 + i);
- msg_pspew(" 0x%02x", readarr[i]);
- }
- msg_pspew("\n");
- return 0;
-}
-
-static int wbsio_spi_read(struct flashctx *flash, uint8_t *buf,
- unsigned int start, unsigned int len)
-{
- mmio_readn((void *)(flash->virtual_memory + start), buf, len);
- return 0;
-}
-
-static int wbsio_spi_shutdown(void *data)
-{
- free(data);
- return 0;
-}
-
-static const struct spi_master spi_master_wbsio = {
- .max_data_read = MAX_DATA_UNSPECIFIED,
- .max_data_write = MAX_DATA_UNSPECIFIED,
- .command = wbsio_spi_send_command,
- .multicommand = default_spi_send_multicommand,
- .map_flash_region = physmap,
- .unmap_flash_region = physunmap,
- .read = wbsio_spi_read,
- .write_256 = spi_chip_write_1,
- .write_aai = spi_chip_write_1,
- .shutdown = wbsio_spi_shutdown,
- .probe_opcode = default_spi_probe_opcode,
-};
-
-int wbsio_check_for_spi(void)
-{
- uint16_t wbsio_spibase = 0;
-
- if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT1)))
- if (0 == (wbsio_spibase = wbsio_get_spibase(WBSIO_PORT2)))
- return 1;
-
- msg_pspew("\nwbsio_spibase = 0x%x\n", wbsio_spibase);
-
- msg_pdbg("%s: Winbond saved on 4 register bits so max chip size is "
- "1024 kB!\n", __func__);
- max_rom_decode.spi = 1024 * 1024;
-
- struct wbsio_spi_data *data = calloc(1, sizeof(*data));
- if (!data) {
- msg_perr("Unable to allocate space for extra SPI master data.\n");
- return SPI_GENERIC_ERROR;
- }
- data->spibase = wbsio_spibase;
-
- return register_spi_master(&spi_master_wbsio, data);
-}
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