Nikolai Artemiev has uploaded this change for review.
[RFC] spi25_statusreg, flashchips: add SR2 read/write support
This patch adds support for reading and writing the second status
register and enables it on a limited set of flash chips.
Chip support for RDSR2/WRSR2/extended WRSR is represented using feature
flags to be consistent with how other SPI capabilities are represented.
BUG=b:195381327,b:153800563
TEST=flashrom --wp-{enable,disable,range,list,status} at end of patch series
TEST=logged SR2 read/write values during wp commands
BRANCH=none
Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
---
M flash.h
M flashchips.c
M spi.h
M spi25_statusreg.c
4 files changed, 48 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/70/58570/1
diff --git a/flash.h b/flash.h
index de66362..448ded8 100644
--- a/flash.h
+++ b/flash.h
@@ -140,6 +140,11 @@
#define FEATURE_ERASED_ZERO (1 << 17)
#define FEATURE_NO_ERASE (1 << 18)
+#define FEATURE_WRSR_EXT (1 << 19)
+#define FEATURE_WRSR2 (1 << 20)
+#define FEATURE_RDSR2 (1 << 21)
+
+
#define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)
enum test_state {
diff --git a/flashchips.c b/flashchips.c
index 434c46d..81523e8 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -6317,7 +6317,8 @@
.total_size = 16384,
.page_size = 256,
/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP |
+ FEATURE_WRSR_EXT | FEATURE_RDSR2,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
@@ -6706,7 +6707,8 @@
.model_id = GIGADEVICE_GD25Q256D,
.total_size = 32768,
.page_size = 256,
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN |
+ FEATURE_WRSR2 | FEATURE_RDSR2,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
@@ -6754,7 +6756,8 @@
.total_size = 4096,
.page_size = 256,
/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP |
+ FEATURE_WRSR2 | FEATURE_RDSR2,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
@@ -6866,7 +6869,8 @@
.total_size = 8192,
.page_size = 256,
/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP |
+ FEATURE_WRSR_EXT | FEATURE_RDSR2,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
diff --git a/spi.h b/spi.h
index 09da579..845b6c2 100644
--- a/spi.h
+++ b/spi.h
@@ -131,6 +131,11 @@
#define JEDEC_RDSR_OUTSIZE 0x01
#define JEDEC_RDSR_INSIZE 0x01
+/* Read Status Register 2 */
+#define JEDEC_RDSR2 0x35
+#define JEDEC_RDSR2_OUTSIZE 0x01
+#define JEDEC_RDSR2_INSIZE 0x01
+
/* Status Register Bits */
#define SPI_SR_WIP (0x01 << 0)
#define SPI_SR_WEL (0x01 << 1)
@@ -146,6 +151,12 @@
#define JEDEC_WRSR 0x01
#define JEDEC_WRSR_OUTSIZE 0x02
#define JEDEC_WRSR_INSIZE 0x00
+#define JEDEC_WRSR_EXT_OUTSIZE 0x03
+
+/* Write Status Register 2 */
+#define JEDEC_WRSR2 0x31
+#define JEDEC_WRSR2_OUTSIZE 0x02
+#define JEDEC_WRSR2_INSIZE 0x00
/* Enter 4-byte Address Mode */
#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 9fb9648..7f631c0 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -91,6 +91,26 @@
write_cmd[1] = value;
write_cmd_len = JEDEC_WRSR_OUTSIZE;
}
+ else if (reg == STATUS2) {
+ if (feature_bits & FEATURE_WRSR_EXT) {
+ /* Writing SR2 with an extended WRSR command requires
+ * writing SR1 along with SR2, so just read SR1 and
+ * write it back. */
+ uint8_t sr1;
+ if (spi_read_register(flash, STATUS1, &sr1))
+ return 1;
+
+ write_cmd[0] = JEDEC_WRSR;
+ write_cmd[1] = sr1;
+ write_cmd[2] = value;
+ write_cmd_len = JEDEC_WRSR_EXT_OUTSIZE;
+ }
+ else if (feature_bits & FEATURE_WRSR2) {
+ write_cmd[0] = JEDEC_WRSR2;
+ write_cmd[1] = value;
+ write_cmd_len = JEDEC_WRSR2_OUTSIZE;
+ }
+ }
if(write_cmd_len == 0) {
msg_cerr("Cannot write register: not supported by chip\n");
return 1;
@@ -112,11 +132,15 @@
int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t *value)
{
+ int feature_bits = flash->chip->feature_bits;
uint8_t read_cmd;
if (reg == STATUS1) {
read_cmd = JEDEC_RDSR;
}
+ else if (reg == STATUS2 && (feature_bits & FEATURE_RDSR2)) {
+ read_cmd = JEDEC_RDSR2;
+ }
else {
msg_cerr("Cannot read register: not supported by chip\n");
return 1;
@@ -125,7 +149,6 @@
/* FIXME: No workarounds for driver/hardware bugs in generic code. */
/* JEDEC_RDSR_INSIZE=1 but wbsio needs 2 */
uint8_t readarr[2];
-
int ret = spi_send_command(
flash, sizeof(read_cmd), sizeof(readarr),
&read_cmd, readarr);
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