Daniel Thompson has posted comments on this change. ( https://review.coreboot.org/26947 )
Change subject: bitbang_spi: Add half-duplex optimizations ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/26947/2/bitbang_spi.c File bitbang_spi.c:
https://review.coreboot.org/#/c/26947/2/bitbang_spi.c@128 PS2, Line 128: if (i == 0) : bitbang_spi_set_sck_set_mosi(master, 0, 0); : else : bitbang_spi_set_sck(master, 0);
I wouldn't expect the state of MOSI to matter. Though, I never read […]
SPI is an ad-hoc standard; very little is defined anywhere!
I assume that the half-duplex protocol used for FLASH is described in a JEDEC document somewhere. Unfortunately so far I haven't found it... so when I developed these patches I worked pretty hard to preserve the existing behaviour as much as possible.
In other words the original code parked MOSI at 0 so this patch does the same thing.
https://review.coreboot.org/#/c/26947/2/bitbang_spi.c@141 PS2, Line 141: uint8_t val)
Nit, we have a 112 chars line limit, so no line break needed here.
Will fix.