Attention is currently required from: Xiang W, Angel Pons.
8 comments:
Patchset:
This implementation is wrong
Not more wrong than yours, however. And it seems easier to fix.
I had a look at it. But before anyone continues, please ask yourself
if this is useful or just a programming excercise. I don't mind the
latter as long as everything is double reviewed and double tested.
File bitbang_spi.c:
Patch Set #1, Line 35: val ^ cpol
This would have to be done in all _set_sck functions?
`val` is misleading; how about `idle` and then set `!idle ^ cpol`?
Tested on my raspberry pi zero with W25Q128.V […]
This aligns with the SCK setting in bitbang_spi_write_byte(). Same
reasoning applies here.
This would be `cpha` too. We want the same edge of the start of any bit.
Patch Set #1, Line 91: bitbang_spi_set_mosi_set_sck(master, (val >> i) & 1, cpha);
So, for CPHA=0 we want to keep SCK in its idle state...
0 ^ CPOL == CPOL => ACK
For CPHA=1 we want to toggle it out of its idle state
1 ^ CPOL = !CPOL => ACK
Patch Set #1, Line 93: bitbang_spi_set_sck(master, !cpha);
Naturally, this works too then.
Patch Set #1, Line 120: bitbang_spi_set_sck(master, 0);
This is only necessary for CPHA=0 and would align nicely with the delay
below in a single if branch.
To view, visit change 49271. To unsubscribe, or for help writing mail filters, visit settings.