Attention is currently required from: David Bartley, Angel Pons.
Patch set 4:Code-Review +1
3 comments:
Patchset:
David, do you happen to have access to the application note about
this chip's dual-die nature? For read status register (in particular
the write-in-progress (WIP) bit), the datasheet refers to the appli-
cation note and the table at 7.3.2 seems to suggest that it depends
on previously executed instructions. That shouldn't be a problem as
we obviously would poll WIP only after accessing the die in question.
But it would be nice to know the details.
Please also provide details in the commit message how you tested
the chip.
File flashchips.c:
Patch Set #1, Line 17757: /* Full chip erase is fastest, typically takes 200s */
I'd be happy with just a flag that reverses the order, since I think we'd want it for normal writes […]
Not sure about a flag. Finding a good solution for the UI might already be
half the effort of fixing flashrom.
Marking this resolved as the erasers are ordered now.
File flashchips.c:
Patch Set #4, Line 17057: FEATURE_4BA
The datasheet doesn't seem to mention an "extended address register"
(read/written with c8/c5). If this is missing, it should be only
FEATURE_4BA_ENTER | FEATURE_4BA_NATIVE
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