Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/flashrom/+/35479 )
Change subject: flashchips.c: Take GD25LQ40 from downstream ......................................................................
flashchips.c: Take GD25LQ40 from downstream
Take definition of GD25LQ40 from ChromiumOS repository. This chip was added in `commit 59543cd1` by dnschneid@chromium.org on 2016-04-27. The commit message notes that some testing had been done, even thought the .tested attribute was left as UNTESTED.
Signed-off-by: Alan Green avg@google.com Change-Id: I978745b38536cda807adf07af4e4d093d0d93ad1 --- M flashchips.c 1 file changed, 2 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/79/35479/1
diff --git a/flashchips.c b/flashchips.c index 5c797fd..ac07fa8 100644 --- a/flashchips.c +++ b/flashchips.c @@ -6009,7 +6009,7 @@ .total_size = 512, .page_size = 256, /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */ - .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, + .feature_bits = FEATURE_WRSR_WREN, .tested = TEST_UNTESTED, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, @@ -6032,8 +6032,7 @@ .block_erase = spi_block_erase_c7, } }, - .printlock = spi_prettyprint_status_register_bp4_srwd, - .unlock = spi_disable_blockprotect_bp4_srwd, /* TODO: 2nd status reg (read with 0x35) */ + .unlock = spi_disable_blockprotect, .write = spi_chip_write_256, .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1695, 1950},