Victor Lim has uploaded this change for review.
flashchips: adding GD25LB512MF/GD25LR512MF
GD25LB512MF: 1.8V 512Mbit shipped with Quad enabled.
https://www.gigadevice.com.cn/Public/Uploads/uploadfile/files/20231213/DS-01012-GD25LB512MF-Rev1.0.pdf
GD25LR512MF: all GD25LB512MF features + RPMC feature
The datasheet is identical with GD25LB512MF for the NOR flash side.
The datasheet is under controll.
You can either refer to GD25LB512MF datasheet.
Or I send you a copy.
Tested with ch347 with erase program read write and protection.
Change-Id: I6a0061a43af5966c93c95645b51a640c00f3d829
Signed-off-by: Victor Lim <vlim@gigadevice.com>
---
M flashchips.c
M include/flashchips.h
2 files changed, 57 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/99/83899/1
diff --git a/flashchips.c b/flashchips.c
index 1198ae4..dd008c2 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -7067,6 +7067,62 @@
},
{
+ .vendor = "GigaDevice",
+ .name = "GD25LB512MF/GD25LR512MF",
+ .bustype = BUS_SPI,
+ .manufacture_id = GIGADEVICE_ID,
+ .model_id = GIGADEVICE_GD25LB512MF,
+ .total_size = 65536,
+ .page_size = 256,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_4BA,
+ .tested = TEST_OK_PREWB,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 16384} },
+ .block_erase = SPI_BLOCK_ERASE_21,
+ }, {
+ .eraseblocks = { {4 * 1024, 16384} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 2048} },
+ .block_erase = SPI_BLOCK_ERASE_5C,
+ }, {
+ .eraseblocks = { {32 * 1024, 2048} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_DC,
+ }, {
+ .eraseblocks = { {64 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {64 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {64 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD,
+ .unlock = SPI_DISABLE_BLOCKPROTECT,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ,
+ .voltage = {1695, 1950},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .tb = {STATUS1, 6, RW},
+ .srl = {STATUS2, 0, RW},
+ .cmp = {STATUS2, 6, RW},
+ },
+ .decode_range = DECODE_RANGE_SPI25,
+ },
+
+ {
.vendor = "GigaDevice",
.name = "GD25LB512ME/GD25LR512ME",
.bustype = BUS_SPI,
diff --git a/include/flashchips.h b/include/flashchips.h
index 5568531..250ade4 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -404,6 +404,7 @@
#define GIGADEVICE_GD25LQ64 0x6017 /* Same as GD25LQ64B (which is faster) */
#define GIGADEVICE_GD25LQ128CD 0x6018
#define GIGADEVICE_GD25LQ255E 0x6019
+#define GIGADEVICE_GD25LB512MF 0x601A /* Same as GD25LR512MF */
#define GIGADEVICE_GD25LF128E 0x6318
#define GIGADEVICE_GD25LF256F 0x6319
#define GIGADEVICE_GD25LR256E 0x6719
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