Attention is currently required from: Robert Zieba, Paul Menzel, Jon Murphy, Edward O'Callaghan, Karthik Ramasubramanian.
1 comment:
File sb600spi.c:
Patch Set #1, Line 574: promontory_read_memmapped(
So this hack was added because reading using SPI commands is very slow compared to using the mmap. […]
since this is also in the public version of the cezanne ppr, i'll just paste it here:
The SPI configuration registers are accessed through SPI base address specified by FCH::LPCPCICFG::spi_base_addr. Software can communicate with the SPI ROM through the default memory or an alternate programming (a.k.a "Indexed mode") method:
• Memory access to the BIOS ROM address space is automatically handled by the hardware. The SPI ROM controller translates the memory address onto the SPI bus and accesses the SPI ROM data. Any other commands besides memory read or memory write to the SPI ROM need to go through the alternate programming (a.k.a "Indexed mode") method. SPI ROM access through the memory address is limited to a 24-bit address (16MB addressable space).
• With the alternate programming (a.k.a "Indexed mode") method, software needs to program the SpiOpCode, SpiAddress, TxByteCount, RxByteCount, put the data into the transmit FIFO, and then execute the command. The hardware communicates with the SPI ROM using these parameters. This alternate programming (a.k.a "Indexed mode") method basically allows software to issue any flash vendor specific commands such as ERASE and STATUS. The alternate programming method can generate up to 32-bit addresses, but transfers are limited to "normal" (1-bit) mode.
i read from that that the indirect access is always in normal spi mode and only the memory mapped reads will use the dual or quad mode. for reads the interface speed is the limiting factor. the prefetching might be another factor. the mmio access is however limited to 16MByte of flash; unsure how this will behave when using 32 bit flash chips
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