David Hendricks has uploaded this change for review.
[WIP] Hack out a lot of stuff
This is for experimentation and should not be used.
Change-Id: Iae8ac4c9006d2f5a488a100e8d878f9069ad7e54
Signed-off-by: David Hendricks <dhendricks@fb.com>
---
M Makefile
M board_enable.c
M chipset_enable.c
M flashchips.c
M internal.c
M print.c
6 files changed, 47 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/57/26657/1
diff --git a/Makefile b/Makefile
index 943d88d..cd27a5a 100644
--- a/Makefile
+++ b/Makefile
@@ -517,10 +517,14 @@
###############################################################################
# Flash chip drivers and bus support infrastructure.
-CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \
- sst28sf040.o 82802ab.o \
- sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \
- opaque.o sfdp.o en29lv640b.o at45db.o
+#CHIP_OBJS = jedec.o stm50.o w39.o w29ee011.o \
+# sst28sf040.o 82802ab.o \
+# sst49lfxxxc.o sst_fwhub.o edi.o flashchips.o spi.o spi25.o spi25_statusreg.o \
+# opaque.o sfdp.o en29lv640b.o at45db.o
+# opaque.o sfdp.o en29lv640b.o at45db.o
+CHIP_OBJS = jedec.o \
+ flashchips.o spi.o spi25.o spi25_statusreg.o \
+ opaque.o sfdp.o
###############################################################################
# Library code.
@@ -737,7 +741,7 @@
FEATURE_CFLAGS += -D'CONFIG_INTERNAL=1'
PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o internal.o
ifeq ($(ARCH), x86)
-PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o amd_imc.o wbsio_spi.o mcp6x_spi.o
+#PROGRAMMER_OBJS += it87spi.o it85spi.o sb600spi.o amd_imc.o wbsio_spi.o mcp6x_spi.o
PROGRAMMER_OBJS += ichspi.o dmi.o
ifeq ($(CONFIG_INTERNAL_DMI), yes)
FEATURE_CFLAGS += -D'CONFIG_INTERNAL_DMI=1'
diff --git a/board_enable.c b/board_enable.c
index a09a075..7e3ffe8 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -28,6 +28,7 @@
#include "hwaccess.h"
#if defined(__i386__) || defined(__x86_64__)
+#if 0
/*
* Helper functions for many Winbond Super I/Os of the W836xx range.
*/
@@ -2256,6 +2257,7 @@
}
#endif
+#endif
/*
* Below is the list of boards which need a special "board enable" code in
@@ -2302,6 +2304,7 @@
/* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */
#if defined(__i386__) || defined(__x86_64__)
+#if 0
{0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
{0x1106, 0x0282, 0x147B, 0x1415, 0x1106, 0x3227, 0x147B, 0x1415, "^AV8 ", NULL, NULL, P3, "abit", "AV8", 0, OK, board_abit_av8},
{0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, NULL /* "^I440BX-W977$" */, "abit", "bf6", P3, "abit", "BF6", 0, OK, intel_piix4_gpo26_lower},
@@ -2475,6 +2478,7 @@
{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
{0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
#endif
+#endif
{ 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */
};
diff --git a/chipset_enable.c b/chipset_enable.c
index 15b760b..6c78cc0 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -39,6 +39,7 @@
#if defined(__i386__) || defined(__x86_64__)
+#if 0
static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
@@ -211,6 +212,7 @@
{
return enable_flash_sis5x0(dev, name, 0x80, 0x40);
}
+#endif
/* Datasheet:
* - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
@@ -946,6 +948,7 @@
return 0;
}
+#if 0
static int via_no_byte_merge(struct pci_dev *dev, const char *name)
{
uint8_t val;
@@ -1598,10 +1601,12 @@
}
#endif
+#endif
/* Please keep this list numerically sorted by vendor/device ID. */
const struct penable chipset_enables[] = {
#if defined(__i386__) || defined(__x86_64__)
+#if 0
{0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
{0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600},
{0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600},
@@ -1714,6 +1719,7 @@
{0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4},
{0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
{0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610},
+#endif
{0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0},
{0x8086, 0x0f1c, OK, "Intel", "Bay Trail", enable_flash_silvermont},
{0x8086, 0x0f1d, NT, "Intel", "Bay Trail", enable_flash_silvermont},
diff --git a/flashchips.c b/flashchips.c
index 8eda608..c33b5b9 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -53,6 +53,7 @@
* .voltage = Voltage range in millivolt
*/
+#if 0
{
.vendor = "AMD",
.name = "Am29F010",
@@ -7419,6 +7420,7 @@
.read = spi_chip_read, /* Fast read (0x0B) supported */
.voltage = {3000, 3600},
},
+#endif
{
.vendor = "Macronix",
@@ -7436,6 +7438,7 @@
.voltage = {3000, 3600},
},
+#if 0
{
.vendor = "Macronix",
.name = "MX25L512(E)/MX25V512(C)",
@@ -8144,6 +8147,7 @@
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600},
},
+#endif
{
.vendor = "Macronix",
@@ -8221,6 +8225,7 @@
.voltage = {2700, 3600},
},
+#if 0
{
.vendor = "Macronix",
.name = "MX25L25635F",
@@ -8443,6 +8448,7 @@
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {1650, 2000},
},
+#endif
{
.vendor = "Macronix",
@@ -8484,6 +8490,7 @@
.voltage = {1650, 2000},
},
+#if 0
{
.vendor = "Macronix",
.name = "MX25L6495F",
@@ -9323,6 +9330,7 @@
.read = spi_chip_read,
.voltage = {2700, 3600},
},
+#endif
{
.vendor = "Micron/Numonyx/ST",
@@ -9353,6 +9361,7 @@
.voltage = {2700, 3600},
},
+#if 0
{
.vendor = "Micron/Numonyx/ST",
.name = "M25PE10",
@@ -9951,6 +9960,7 @@
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600},
},
+#endif
{
.vendor = "Micron/Numonyx/ST",
@@ -10018,6 +10028,7 @@
.voltage = {2700, 3600},
},
+#if 0
{
.vendor = "Micron",
.name = "N25Q256..3E/MT25QL256", /* ..3E/L = 3V, uniform 64KB/4KB blocks/sectors */
@@ -12014,6 +12025,7 @@
.read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */
.voltage = {2700, 3600},
},
+#endif
{
.vendor = "Spansion",
@@ -12309,6 +12321,7 @@
.voltage = {2700, 3600},
},
+#if 0
{
.vendor = "SST",
.name = "SST25LF020A",
@@ -15014,6 +15027,7 @@
.voltage = {2700, 3600},
},
+#endif
{
.vendor = "Winbond",
.name = "W25Q128.V",
@@ -15053,6 +15067,7 @@
.read = spi_chip_read,
.voltage = {2700, 3600},
},
+#if 0
{
.vendor = "Winbond",
@@ -15410,6 +15425,7 @@
.read = spi_chip_read,
.voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */
},
+#endif
{
.vendor = "Winbond",
@@ -15451,6 +15467,7 @@
.voltage = {1650, 1950},
},
+#if 0
{
.vendor = "Winbond",
.name = "W25X10",
@@ -16669,6 +16686,7 @@
.read = spi_chip_read,
.voltage = {2700, 3600},
},
+#endif
{
.vendor = "Unknown",
diff --git a/internal.c b/internal.c
index 1d6cff6..080a0b4 100644
--- a/internal.c
+++ b/internal.c
@@ -94,6 +94,7 @@
int force_boardmismatch = 0;
#if IS_X86
+#if 0
void probe_superio(void)
{
probe_superio_winbond();
@@ -105,6 +106,7 @@
//probe_superio_smsc();
probe_superio_ite();
}
+#endif
int superio_count = 0;
#define SUPERIO_MAX_COUNT 3
@@ -263,7 +265,9 @@
board_handle_before_superio();
/* Probe for the Super I/O chip and fill global struct superio. */
+#if 0
probe_superio();
+#endif
#else
/* FIXME: Enable cbtable searching on all non-x86 platforms supported
* by coreboot.
@@ -319,7 +323,9 @@
#if IS_X86
/* Probe unconditionally for ITE Super I/O chips. This enables LPC->SPI translation on IT87* and
* parallel writes on IT8705F. Also, this handles the manual chip select for Gigabyte's DualBIOS. */
+#if 0
init_superio_ite();
+#endif
if (board_flash_enable(board_vendor, board_model, cb_vendor, cb_model)) {
msg_perr("Aborting to be safe.\n");
diff --git a/print.c b/print.c
index 114181e..799c7da 100644
--- a/print.c
+++ b/print.c
@@ -515,6 +515,7 @@
/* Please keep this list alphabetically ordered by vendor/board. */
const struct board_info boards_known[] = {
#if defined(__i386__) || defined(__x86_64__)
+#if 0
B("A-Trend", "ATC-6220", OK, "http://www.motherboard.cz/mb/atrend/atc6220.htm", NULL),
B("abit", "A-S78H", OK, NULL, NULL),
B("abit", "AN-M2", OK, NULL, NULL),
@@ -1136,6 +1137,7 @@
B("ZOTAC", "ZBOX AD02 (PLUS)", OK, NULL, NULL),
B("ZOTAC", "ZBOX HD-ID11", OK, NULL, NULL),
#endif
+#endif
{0},
};
@@ -1143,6 +1145,7 @@
/* Please keep this list alphabetically ordered by vendor/board. */
const struct board_info laptops_known[] = {
#if defined(__i386__) || defined(__x86_64__)
+#if 0
B("Acer", "Aspire 1520", OK, "http://support.acer.com/us/en/acerpanam/notebook/0000/Acer/Aspire1520/Aspire1520nv.shtml", NULL),
B("Acer", "Aspire One", BAD, NULL, "http://www.coreboot.org/pipermail/coreboot/2009-May/048041.html"),
B("ASUS", "A8Jm", OK, NULL, NULL),
@@ -1170,7 +1173,7 @@
//B("MSI", "GT60-2OD", OK, "http://www.msi.com/product/nb/GT60_2OD.html", NULL), requires layout patches
B("Teclast", "X98 Air 3G", OK, NULL, NULL),
#endif
-
+#endif
{0},
};
#endif
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