Edward O'Callaghan submitted this change.
board_enable.c: Port to use pcidev_find_vendorclass() helper
Change-Id: I3d8e3dbd5eeb057d7c959a82678cca2345fc69d9
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/62405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
---
M board_enable.c
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/board_enable.c b/board_enable.c
index d740806..7b9e9f6 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -1555,26 +1555,20 @@
int i, allowed;
/* First, look for a known LPC bridge */
- for (dev = pacc->devices; dev; dev = dev->next) {
- uint16_t device_class;
- /* libpci before version 2.2.4 does not store class info. */
- device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
- if ((dev->vendor_id == 0x8086) &&
- (device_class == 0x0601)) { /* ISA bridge */
- /* Is this device in our list? */
- for (i = 0; intel_ich_gpio_table[i].id; i++)
- if (dev->device_id == intel_ich_gpio_table[i].id)
- break;
-
- if (intel_ich_gpio_table[i].id)
- break;
- }
- }
-
+ dev = pcidev_find_vendorclass(0x8086, 0x0601); /* ISA bridge */
if (!dev) {
msg_perr("\nERROR: No known Intel LPC bridge found.\n");
return -1;
}
+ /* Is this device in our list? */
+ for (i = 0; intel_ich_gpio_table[i].id; i++)
+ if (dev->device_id == intel_ich_gpio_table[i].id)
+ break;
+
+ if (!intel_ich_gpio_table[i].id) {
+ msg_perr("\nERROR: No known Intel LPC bridge found.\n");
+ return -1;
+ }
/*
* According to the datasheets, all Intel ICHs have the GPIO bar 5:1
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