Edward O'Callaghan has uploaded this change for review.
max_rom_decode packed into cfg WIP
Change-Id: If1dd6013594d7e1a50658afb1fde8d1e191ee443
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M atapromise.c
M chipset_enable.c
M cli_classic.c
M drkaiser.c
M flashrom.c
M include/programmer.h
M it8212.c
M nic3com.c
M nicintel.c
M nicnatsemi.c
M satamv.c
11 files changed, 33 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/22/67322/1
diff --git a/atapromise.c b/atapromise.c
index 63463f5..08ce499 100644
--- a/atapromise.c
+++ b/atapromise.c
@@ -181,7 +181,7 @@
data->bar = bar;
data->rom_size = rom_size;
- max_rom_decode.parallel = rom_size;
+ cfg->max_rom_decode.parallel = rom_size;
return register_par_master(&par_master_atapromise, BUS_PARALLEL, data);
}
diff --git a/chipset_enable.c b/chipset_enable.c
index e205a83..3c62efe 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1238,18 +1238,18 @@
reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
if (reg8 & CS5530_ISA_MASTER) {
/* We have A0-A23 available. */
- max_rom_decode.parallel = 16 * 1024 * 1024;
+ cfg->max_rom_decode.parallel = 16 * 1024 * 1024;
} else {
reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
if (reg8 & CS5530_ENABLE_SA2320) {
/* We have A0-19, A20-A23 available. */
- max_rom_decode.parallel = 16 * 1024 * 1024;
+ cfg->max_rom_decode.parallel = 16 * 1024 * 1024;
} else if (reg8 & CS5530_ENABLE_SA20) {
/* We have A0-19, A20 available. */
- max_rom_decode.parallel = 2 * 1024 * 1024;
+ cfg->max_rom_decode.parallel = 2 * 1024 * 1024;
} else {
/* A20 and above are not active. */
- max_rom_decode.parallel = 1024 * 1024;
+ cfg->max_rom_decode.parallel = 1024 * 1024;
}
}
@@ -1355,14 +1355,14 @@
static int enable_flash_amd_768_8111(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
{
/* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */
- max_rom_decode.lpc = 5 * 1024 * 1024;
+ cfg->max_rom_decode.lpc = 5 * 1024 * 1024;
return enable_flash_amd_via(cfg, dev, name, 0xC0);
}
static int enable_flash_vt82c586(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
{
/* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */
- max_rom_decode.parallel = 512 * 1024;
+ cfg->max_rom_decode.parallel = 512 * 1024;
return enable_flash_amd_via(cfg, dev, name, 0xC0);
}
@@ -1370,7 +1370,7 @@
static int enable_flash_vt82c596(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
{
/* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */
- max_rom_decode.parallel = 1024 * 1024;
+ cfg->max_rom_decode.parallel = 1024 * 1024;
return enable_flash_amd_via(cfg, dev, name, 0xE0);
}
diff --git a/cli_classic.c b/cli_classic.c
index bac31d1..91578d2 100644
--- a/cli_classic.c
+++ b/cli_classic.c
@@ -1014,7 +1014,7 @@
print_chip_support_status(fill_flash->chip);
- unsigned int limitexceeded = count_max_decode_exceedings(fill_flash);
+ unsigned int limitexceeded = count_max_decode_exceedings(fill_flash); // XXX
if (limitexceeded > 0 && !force) {
enum chipbustype commonbuses = fill_flash->mst->buses_supported & fill_flash->chip->bustype;
diff --git a/drkaiser.c b/drkaiser.c
index b121eec..18eafea 100644
--- a/drkaiser.c
+++ b/drkaiser.c
@@ -112,7 +112,7 @@
data->flash_access = pci_read_word(dev, PCI_MAGIC_DRKAISER_ADDR);
pci_write_word(dev, PCI_MAGIC_DRKAISER_ADDR, PCI_MAGIC_DRKAISER_VALUE);
- max_rom_decode.parallel = 128 * 1024;
+ cfg->max_rom_decode.parallel = 128 * 1024;
return register_par_master(&par_master_drkaiser, BUS_PARALLEL, data);
}
diff --git a/flashrom.c b/flashrom.c
index 6c38e62..79b4f0c 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -38,12 +38,6 @@
static const struct programmer_entry *programmer = NULL;
-/*
- * Programmers supporting multiple buses can have differing size limits on
- * each bus. Store the limits for each bus in a common struct.
- */
-struct decode_sizes max_rom_decode;
-
/* If nonzero, used as the start address of bottom-aligned flash. */
unsigned long flashbase;
@@ -67,6 +61,11 @@
struct programmer_cfg {
char *params;
+ /*
+ * Programmers supporting multiple buses can have differing size limits on
+ * each bus. Store the limits for each bus in a common struct.
+ */
+ struct decode_sizes max_rom_decode;
};
/* Register a function to be executed on programmer shutdown.
@@ -153,7 +152,7 @@
programmer = prog;
/* Initialize all programmer specific data. */
/* Default to unlimited decode sizes. */
- max_rom_decode = (const struct decode_sizes) {
+ struct decode_sizes max_rom_decode = (const struct decode_sizes) {
.parallel = 0xffffffff,
.lpc = 0xffffffff,
.fwh = 0xffffffff,
@@ -167,7 +166,7 @@
programmer_may_write = 1;
msg_pdbg("Initializing %s programmer\n", prog->name);
- const struct programmer_cfg cfg = { .params = strdup(param) };
+ const struct programmer_cfg cfg = { .params = strdup(param), .max_rom_decode = max_rom_decode };
int ret = prog->init(&cfg);
ret = get_param_residue(cfg.params, ret);
free(cfg.params);
diff --git a/include/programmer.h b/include/programmer.h
index 5331a12..0186399 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -284,7 +284,6 @@
uint32_t spi;
};
// FIXME: These need to be local, not global
-extern struct decode_sizes max_rom_decode;
extern int programmer_may_write;
extern unsigned long flashbase;
unsigned int count_max_decode_exceedings(const struct flashctx *flash);
diff --git a/it8212.c b/it8212.c
index 18d1173..1adf9a9 100644
--- a/it8212.c
+++ b/it8212.c
@@ -103,7 +103,7 @@
data->decode_access = pci_read_long(dev, PCI_ROM_ADDRESS);
pci_write_long(dev, PCI_ROM_ADDRESS, io_base_addr | 0x01);
- max_rom_decode.parallel = IT8212_MEMMAP_SIZE;
+ cfg->max_rom_decode.parallel = IT8212_MEMMAP_SIZE;
return register_par_master(&par_master_it8212, BUS_PARALLEL, data);
}
const struct programmer_entry programmer_it8212 = {
diff --git a/nic3com.c b/nic3com.c
index 44710ed..9fb0035 100644
--- a/nic3com.c
+++ b/nic3com.c
@@ -148,7 +148,7 @@
data->internal_conf = internal_conf;
data->id = id;
- max_rom_decode.parallel = 128 * 1024;
+ cfg->max_rom_decode.parallel = 128 * 1024;
return register_par_master(&par_master_nic3com, BUS_PARALLEL, data);
diff --git a/nicintel.c b/nicintel.c
index 16cb5e4..ff47e56 100644
--- a/nicintel.c
+++ b/nicintel.c
@@ -124,7 +124,7 @@
data->nicintel_bar = bar;
data->nicintel_control_bar = control_bar;
- max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
+ cfg->max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;
return register_par_master(&par_master_nicintel, BUS_PARALLEL, data);
}
diff --git a/nicnatsemi.c b/nicnatsemi.c
index 779fb33..44dfdd9 100644
--- a/nicnatsemi.c
+++ b/nicnatsemi.c
@@ -114,10 +114,10 @@
/* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15
* in another. My NIC has MA16 connected to A16 on the boot ROM socket
* so I'm assuming it is accessible. If not then next line wants to be
- * max_rom_decode.parallel = 65536; and the mask in the read/write
+ * cfg->max_rom_decode.parallel = 65536; and the mask in the read/write
* functions below wants to be 0x0000FFFF.
*/
- max_rom_decode.parallel = 131072;
+ cfg->max_rom_decode.parallel = 131072;
return register_par_master(&par_master_nicnatsemi, BUS_PARALLEL, data);
}
diff --git a/satamv.c b/satamv.c
index f886076..915d80f 100644
--- a/satamv.c
+++ b/satamv.c
@@ -202,7 +202,7 @@
/* 512 kByte with two 8-bit latches, and
* 4 MByte with additional 3-bit latch. */
- max_rom_decode.parallel = 4 * 1024 * 1024;
+ cfg->max_rom_decode.parallel = 4 * 1024 * 1024;
return register_par_master(&par_master_satamv, BUS_PARALLEL, data);
}
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