garyodernichts@gmail.com has uploaded this change for review.
flashchips/micron: Not all N25QL256 support 4BA_WRITE
According to the Micron N25Q256A 3V datasheet:
> This command is only for part numbers N25Q256A83ESF40x, N25Q256A83E1240x, and
N25Q256A83ESFA0F.
Since there are other chips with the N25Q256 rdid (0xBA19), it is not safe to assume that all chips support 4BA_WRITE.
When testing this on a 25Q256, the 4BA_WRITE command behaved more like an erase by writing all 0xFFs.
With the patch, which is now using the default page program operation, it works fine.
Change-Id: I3af103a99139705f6549369ed5af76a6197c3362
Signed-off-by: GaryOderNichts <garyodernichts@gmail.com>
---
M flashchips/micron.c
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/69/85869/1
diff --git a/flashchips/micron.c b/flashchips/micron.c
index 5b49892..08b3521 100644
--- a/flashchips/micron.c
+++ b/flashchips/micron.c
@@ -292,7 +292,8 @@
.page_size = 256,
/* supports SFDP */
/* OTP: 64B total; read 0x4B, write 0x42 */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_WREN,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA_ENTER_WREN |
+ FEATURE_4BA_EAR_C5C8 | FEATURE_4BA_READ | FEATURE_4BA_FAST_READ,
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
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