Edward O'Callaghan has uploaded this change for review.
chipset_enable.c: plumb max_rom_decodes from internal.c
Change-Id: If2692f272fb454a200a238109178e48857964439
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
---
M chipset_enable.c
M include/programmer.h
M internal.c
3 files changed, 114 insertions(+), 103 deletions(-)
git pull ssh://review.coreboot.org:29418/flashrom refs/changes/76/68676/1
diff --git a/chipset_enable.c b/chipset_enable.c
index d6103c1..a5f0c42 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -44,7 +44,7 @@
#include "hwaccess_x86_io.h"
#include "hwaccess_x86_msr.h"
-static int enable_flash_ali_m1533(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_ali_m1533(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint8_t tmp;
@@ -59,7 +59,7 @@
return 0;
}
-static int enable_flash_rdc_r8610(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_rdc_r8610(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint8_t tmp;
@@ -85,7 +85,7 @@
return 0;
}
-static int enable_flash_sis85c496(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_sis85c496(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint8_t tmp;
@@ -135,7 +135,7 @@
return sbdev;
}
-static int enable_flash_sis501(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_sis501(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint8_t tmp;
int ret = 0;
@@ -160,7 +160,7 @@
return ret;
}
-static int enable_flash_sis5511(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_sis5511(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint8_t tmp;
int ret = 0;
@@ -207,12 +207,12 @@
return ret;
}
-static int enable_flash_sis530(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_sis530(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_sis5x0(cfg, dev, name, 0x20, 0x04);
}
-static int enable_flash_sis540(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_sis540(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_sis5x0(cfg, dev, name, 0x80, 0x40);
}
@@ -223,7 +223,7 @@
* - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
* - Order Number: 290562-001
*/
-static int enable_flash_piix4(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_piix4(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint16_t old, new;
uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
@@ -380,7 +380,7 @@
return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0);
}
-static int enable_flash_ich_fwh_decode(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation)
+static int enable_flash_ich_fwh_decode(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation, struct decode_sizes *max_rom_decode_)
{
uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */
bool implemented = 0;
@@ -549,42 +549,42 @@
contiguous = 0;
}
}
- max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
- msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh);
+ max_rom_decode_->fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
+ msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode_->fwh);
return 0;
}
-static int enable_flash_ich_fwh(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
+static int enable_flash_ich_fwh(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl, struct decode_sizes *max_rom_decode_)
{
int err;
/* Configure FWH IDSEL decoder maps. */
- if ((err = enable_flash_ich_fwh_decode(cfg, dev, ich_generation)) != 0)
+ if ((err = enable_flash_ich_fwh_decode(cfg, dev, ich_generation, max_rom_decode_)) != 0)
return err;
internal_buses_supported &= BUS_FWH;
return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl);
}
-static int enable_flash_ich0(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_ich0(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH, 0x4e);
+ return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH, 0x4e, max_rom_decode_);
}
-static int enable_flash_ich2345(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_ich2345(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH2345, 0x4e);
+ return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH2345, 0x4e, max_rom_decode_);
}
-static int enable_flash_ich6(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_ich6(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH6, 0xdc);
+ return enable_flash_ich_fwh(cfg, dev, CHIPSET_ICH6, 0xdc, max_rom_decode_);
}
-static int enable_flash_poulsbo(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_poulsbo(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_fwh(cfg, dev, CHIPSET_POULSBO, 0xd8);
+ return enable_flash_ich_fwh(cfg, dev, CHIPSET_POULSBO, 0xd8, max_rom_decode_);
}
static enum chipbustype enable_flash_ich_report_gcs(
@@ -770,7 +770,7 @@
return boot_straps[bbs].bus;
}
-static int enable_flash_ich_spi(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
+static int enable_flash_ich_spi(const struct programmer_cfg *cfg, struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl, struct decode_sizes *max_rom_decode_)
{
/* Get physical address of Root Complex Register Block */
uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000;
@@ -784,7 +784,7 @@
const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
/* Handle FWH-related parameters and initialization */
- int ret_fwh = enable_flash_ich_fwh(cfg, dev, ich_generation, bios_cntl);
+ int ret_fwh = enable_flash_ich_fwh(cfg, dev, ich_generation, bios_cntl, max_rom_decode_);
if (ret_fwh == ERROR_FATAL)
return ret_fwh;
@@ -831,82 +831,82 @@
return 0;
}
-static int enable_flash_tunnelcreek(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_tunnelcreek(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_TUNNEL_CREEK, 0xd8);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_TUNNEL_CREEK, 0xd8, max_rom_decode_);
}
-static int enable_flash_s12x0(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_s12x0(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_CENTERTON, 0xd8);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_CENTERTON, 0xd8, max_rom_decode_);
}
-static int enable_flash_ich7(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_ich7(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH7, 0xdc);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH7, 0xdc, max_rom_decode_);
}
-static int enable_flash_ich8(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_ich8(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH8, 0xdc);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH8, 0xdc, max_rom_decode_);
}
-static int enable_flash_ich9(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_ich9(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH9, 0xdc);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH9, 0xdc, max_rom_decode_);
}
-static int enable_flash_ich10(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_ich10(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH10, 0xdc);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_ICH10, 0xdc, max_rom_decode_);
}
/* Ibex Peak aka. 5 series & 3400 series */
-static int enable_flash_pch5(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_pch5(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc, max_rom_decode_);
}
/* Cougar Point aka. 6 series & c200 series */
-static int enable_flash_pch6(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_pch6(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc, max_rom_decode_);
}
/* Panther Point aka. 7 series */
-static int enable_flash_pch7(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_pch7(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc, max_rom_decode_);
}
/* Lynx Point aka. 8 series */
-static int enable_flash_pch8(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_pch8(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc, max_rom_decode_);
}
/* Lynx Point LP aka. 8 series low-power */
-static int enable_flash_pch8_lp(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_pch8_lp(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc, max_rom_decode_);
}
/* Wellsburg (for Haswell-EP Xeons) */
-static int enable_flash_pch8_wb(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_pch8_wb(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc, max_rom_decode_);
}
/* Wildcat Point */
-static int enable_flash_pch9(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_pch9(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc, max_rom_decode_);
}
/* Wildcat Point LP */
-static int enable_flash_pch9_lp(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_pch9_lp(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
- return enable_flash_ich_spi(cfg, dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc);
+ return enable_flash_ich_spi(cfg, dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc, max_rom_decode_);
}
/* Sunrise Point */
@@ -979,57 +979,57 @@
return ret;
}
-static int enable_flash_pch100(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
+static int enable_flash_pch100(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT);
}
-static int enable_flash_c620(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
+static int enable_flash_c620(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG);
}
-static int enable_flash_pch300(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
+static int enable_flash_pch300(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT);
}
-static int enable_flash_pch400(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
+static int enable_flash_pch400(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_400_SERIES_COMET_POINT);
}
-static int enable_flash_pch500(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
+static int enable_flash_pch500(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT);
}
-static int enable_flash_pch600(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
+static int enable_flash_pch600(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_600_SERIES_ALDER_POINT);
}
-static int enable_flash_mtl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
+static int enable_flash_mtl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_METEOR_LAKE);
}
-static int enable_flash_mcc(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
+static int enable_flash_mcc(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE);
}
-static int enable_flash_jsl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
+static int enable_flash_jsl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x1f, 5, CHIPSET_JASPER_LAKE);
}
-static int enable_flash_apl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
+static int enable_flash_apl(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
}
-static int enable_flash_glk(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name)
+static int enable_flash_glk(const struct programmer_cfg *cfg, struct pci_dev *const dev, const char *const name, struct decode_sizes *max_rom_decode_)
{
return enable_flash_pch100_or_c620(cfg, dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE);
}
@@ -1044,7 +1044,7 @@
* - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800).
* - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC).
*/
-static int enable_flash_silvermont(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_silvermont(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
enum ich_chipset ich_generation = CHIPSET_BAYTRAIL;
@@ -1060,7 +1060,7 @@
physunmap(rcrb, 4);
/* Handle fwh_idsel parameter */
- int ret_fwh = enable_flash_ich_fwh_decode(cfg, dev, ich_generation);
+ int ret_fwh = enable_flash_ich_fwh_decode(cfg, dev, ich_generation, max_rom_decode_);
if (ret_fwh == ERROR_FATAL)
return ret_fwh;
@@ -1092,7 +1092,7 @@
return 0;
}
-static int via_no_byte_merge(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int via_no_byte_merge(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint8_t val;
@@ -1105,7 +1105,7 @@
return NOT_DONE_YET; /* need to find south bridge, too */
}
-static int enable_flash_vt823x(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_vt823x(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint8_t val;
@@ -1132,7 +1132,7 @@
return 0;
}
-static int enable_flash_vt_vx(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_vt_vx(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
struct pci_dev *south_north = pcidev_find(0x1106, 0xa353);
if (south_north == NULL) {
@@ -1143,7 +1143,7 @@
msg_pdbg("Strapped to ");
if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) {
msg_pdbg("LPC.\n");
- return enable_flash_vt823x(cfg, dev, name);
+ return enable_flash_vt823x(cfg, dev, name, max_rom_decode_);
}
msg_pdbg("SPI.\n");
@@ -1196,12 +1196,12 @@
return via_init_spi(spi0_mm_base);
}
-static int enable_flash_vt8237s_spi(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_vt8237s_spi(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
return via_init_spi(pci_read_long(dev, 0xbc) << 8);
}
-static int enable_flash_cs5530(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_cs5530(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint8_t reg8;
@@ -1239,18 +1239,18 @@
reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
if (reg8 & CS5530_ISA_MASTER) {
/* We have A0-A23 available. */
- max_rom_decode.parallel = 16 * 1024 * 1024;
+ max_rom_decode_->parallel = 16 * 1024 * 1024;
} else {
reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
if (reg8 & CS5530_ENABLE_SA2320) {
/* We have A0-19, A20-A23 available. */
- max_rom_decode.parallel = 16 * 1024 * 1024;
+ max_rom_decode_->parallel = 16 * 1024 * 1024;
} else if (reg8 & CS5530_ENABLE_SA20) {
/* We have A0-19, A20 available. */
- max_rom_decode.parallel = 2 * 1024 * 1024;
+ max_rom_decode_->parallel = 2 * 1024 * 1024;
} else {
/* A20 and above are not active. */
- max_rom_decode.parallel = 1024 * 1024;
+ max_rom_decode_->parallel = 1024 * 1024;
}
}
@@ -1265,7 +1265,7 @@
* To enable write to NOR Boot flash for the benefit of systems that have such
* a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
*/
-static int enable_flash_cs5536(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_cs5536(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
#define MSR_RCONF_DEFAULT 0x1808
#define MSR_NORF_CTL 0x51400018
@@ -1294,7 +1294,7 @@
return 0;
}
-static int enable_flash_sc1100(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_sc1100(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
#define SC_REG 0x52
uint8_t new;
@@ -1353,29 +1353,29 @@
return 0;
}
-static int enable_flash_amd_768_8111(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_amd_768_8111(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
/* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */
- max_rom_decode.lpc = 5 * 1024 * 1024;
+ max_rom_decode_->lpc = 5 * 1024 * 1024;
return enable_flash_amd_via(cfg, dev, name, 0xC0);
}
-static int enable_flash_vt82c586(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_vt82c586(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
/* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */
- max_rom_decode.parallel = 512 * 1024;
+ max_rom_decode_->parallel = 512 * 1024;
return enable_flash_amd_via(cfg, dev, name, 0xC0);
}
/* Works for VT82C686A/B too. */
-static int enable_flash_vt82c596(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_vt82c596(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
/* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */
- max_rom_decode.parallel = 1024 * 1024;
+ max_rom_decode_->parallel = 1024 * 1024;
return enable_flash_amd_via(cfg, dev, name, 0xE0);
}
-static int enable_flash_sb600(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_sb600(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint32_t prot;
uint8_t reg;
@@ -1466,7 +1466,7 @@
return 0;
}
-static int enable_flash_nvidia_nforce2(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_nvidia_nforce2(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
rpci_write_byte(dev, 0x92, 0);
if (enable_flash_nvidia_common(cfg, dev, name))
@@ -1475,7 +1475,7 @@
return 0;
}
-static int enable_flash_ck804(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_ck804(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint32_t segctrl;
uint8_t reg, old, new;
@@ -1550,7 +1550,7 @@
return 0;
}
-static int enable_flash_osb4(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_osb4(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint8_t tmp;
@@ -1568,7 +1568,7 @@
}
/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
-static int enable_flash_sb400(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_sb400(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint8_t tmp;
struct pci_dev *smbusdev;
@@ -1603,7 +1603,7 @@
return 0;
}
-static int enable_flash_mcp55(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_mcp55(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint8_t val;
uint16_t wordval;
@@ -1630,7 +1630,7 @@
* It is assumed that LPC chips need the MCP55 code and SPI chips need the
* code provided in enable_flash_mcp6x_7x_common.
*/
-static int enable_flash_mcp6x_7x(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_mcp6x_7x(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
int ret = 0, want_spi = 0;
uint8_t val;
@@ -1642,7 +1642,7 @@
switch ((val >> 5) & 0x3) {
case 0x0:
- ret = enable_flash_mcp55(cfg, dev, name);
+ ret = enable_flash_mcp55(cfg, dev, name, max_rom_decode_);
internal_buses_supported &= BUS_LPC;
msg_pdbg("Flash bus type is LPC\n");
break;
@@ -1681,7 +1681,7 @@
return ret;
}
-static int enable_flash_ht1000(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int enable_flash_ht1000(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
uint8_t val;
@@ -1704,7 +1704,7 @@
* complete flash is mapped somewhere below 1G. The position can be determined
* by the BOOTCS PAR register.
*/
-static int get_flashbase_sc520(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name)
+static int get_flashbase_sc520(const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_)
{
int i, bootcs_found = 0;
uint32_t parx = 0;
@@ -2183,7 +2183,7 @@
{0},
};
-int chipset_flash_enable(const struct programmer_cfg *cfg)
+int chipset_flash_enable(const struct programmer_cfg *cfg, struct decode_sizes *max_rom_decode_)
{
struct pci_dev *dev = NULL;
int ret = -2; /* Nothing! */
@@ -2232,7 +2232,7 @@
continue;
}
msg_pinfo("Enabling flash write... ");
- ret = chipset_enables[i].doit(cfg, dev, chipset_enables[i].device_name);
+ ret = chipset_enables[i].doit(cfg, dev, chipset_enables[i].device_name, max_rom_decode_);
if (ret == NOT_DONE_YET) {
ret = -2;
msg_pinfo("OK - searching further chips.\n");
diff --git a/include/programmer.h b/include/programmer.h
index d5338d9..4da7330 100644
--- a/include/programmer.h
+++ b/include/programmer.h
@@ -32,6 +32,13 @@
};
struct programmer_cfg;
+struct decode_sizes {
+ uint32_t parallel;
+ uint32_t lpc;
+ uint32_t fwh;
+ uint32_t spi;
+};
+
struct dev_entry {
uint16_t vendor_id;
uint16_t device_id;
@@ -149,7 +156,7 @@
const enum test_state status;
const char *vendor_name;
const char *device_name;
- int (*doit) (const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name);
+ int (*doit) (const struct programmer_cfg *cfg, struct pci_dev *dev, const char *name, struct decode_sizes *max_rom_decode_);
};
extern const struct penable chipset_enables[];
@@ -231,7 +238,7 @@
struct decode_sizes *max_rom_decode_);
/* chipset_enable.c */
-int chipset_flash_enable(const struct programmer_cfg *cfg);
+int chipset_flash_enable(const struct programmer_cfg *cfg, struct decode_sizes *);
/* processor_enable.c */
int processor_flash_enable(void);
@@ -277,12 +284,6 @@
/* flashrom.c */
-struct decode_sizes {
- uint32_t parallel;
- uint32_t lpc;
- uint32_t fwh;
- uint32_t spi;
-};
// FIXME: These need to be local, not global
extern struct decode_sizes max_rom_decode;
extern bool programmer_may_write;
diff --git a/internal.c b/internal.c
index a4710ee..1b3b8b0 100644
--- a/internal.c
+++ b/internal.c
@@ -285,7 +285,7 @@
/* try to enable it. Failure IS an option, since not all motherboards
* really need this to be done, etc., etc.
*/
- ret = chipset_flash_enable(cfg);
+ ret = chipset_flash_enable(cfg, &max_rom_decode);
if (ret == -2) {
msg_perr("WARNING: No chipset found. Flash detection "
"will most likely fail.\n");
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