Anastasia Klimchuk submitted this change.

View Change

Approvals: Anastasia Klimchuk: Looks good to me, approved build bot (Jenkins): Verified
flashchips: Correct feature_bits for MX25L128*

In CB:81792 (CL:5471748) we add write-protect support for MX25L12833F,
MX25L12835F/MX25L12873F, and MX25L12845E/MX25L12865E.

However, that CL contained a bug that it didn't set the feature_bits
correctly. We need to add:

* Add FEATURE_CFGR and FEATURE_SCUR for MX25L12833F
* Add FEATURE_CFGR and FEATURE_SCUR for MX25L12835F/MX25L12873F
* Add FEATURE_SCUR for MX25L12845E/MX25L12865E

BUG=b:332486637
TEST=In a host connect to ADL-n ChromeOS via servo, with this patch,
flashrom -p raiden_debug_spi:target=AP,custom_rst=true
,serial=$(dut-control -o ccd_serialname -p 9996) --wp-status
returns correct WP status.
TEST=without this patch, returns error with
"Cannot read SECURITY: unsupported by chip"

Change-Id: I001cde6816bd099317bc9c23904c5fcbe6003241
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82605
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
M flashchips.c
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/flashchips.c b/flashchips.c
index 776b3a8..2065746 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -9209,7 +9209,7 @@
.total_size = 16384,
.page_size = 256,
/* OTP: 1KB total; enter 0xB1, exit 0xC1 */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR | FEATURE_SCUR,
.tested = TEST_OK_PREWB,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
@@ -9256,7 +9256,7 @@
.total_size = 16384,
.page_size = 256,
/* OTP: 512B total; enter 0xB1, exit 0xC1 */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR | FEATURE_SCUR,
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
@@ -9303,7 +9303,7 @@
.total_size = 16384,
.page_size = 256,
/* OTP: 512B total; enter 0xB1, exit 0xC1 */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_SCUR,
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,

To view, visit change 82605. To unsubscribe, or for help writing mail filters, visit settings.

Gerrit-MessageType: merged
Gerrit-Project: flashrom
Gerrit-Branch: main
Gerrit-Change-Id: I001cde6816bd099317bc9c23904c5fcbe6003241
Gerrit-Change-Number: 82605
Gerrit-PatchSet: 2
Gerrit-Owner: Hsuan-ting Chen <roccochen@google.com>
Gerrit-Reviewer: Anastasia Klimchuk <aklm@chromium.org>
Gerrit-Reviewer: Hsuan Ting Chen <roccochen@chromium.org>
Gerrit-Reviewer: Nikolai Artemiev <nartemiev@google.com>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer@coreboot.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>