Alexandru Stan has uploaded this change for review.

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WIP: flashchips: add Winbond W25R512NWEIQ

I don't actually have a datasheet for this (so feel free to reject this
CL), I just bruteforced it by looking at the chip IDs and knowing it's
a 64M chip.

I used W25Q256JW as a template and just increased every erase size
calculation.

I tested it by running:
dd if=/dev/urandom of=/tmp/random.bin bs=1M count=64
sudo /tmp/flashrom/build/flashrom -p ft2232_spi:type=2232H -w /tmp/random.bin --progress
sudo /tmp/flashrom/build/flashrom -p ft2232_spi:type=2232H -v /tmp/random.bin
And I saw "Verifying flash... VERIFIED."
PS: Yes I know I probably overvolted the chip by giving it 3.3V

Change-Id: Ibf670e4014a22e4636789768b759cb51f75cd046
Signed-off-by: Alexandru M Stan <ams@frame.work>
---
M flashchips.c
M include/flashchips.h
2 files changed, 47 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/flashrom refs/changes/52/84752/1

diff --git a/flashchips.c b/flashchips.c
index 02eefa4..c294e63 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -20227,6 +20227,52 @@
 
 	{
 		.vendor		= "Winbond",
+		.name		= "W25R512NWEIQ",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= WINBOND_NEX_ID,
+		.model_id	= WINBOND_NEX_W25R512NWEIQ,
+		.total_size	= 65536,
+		.page_size	= 256,
+		/* supports SFDP */
+		/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
+		.tested		= TEST_OK_PREW,
+		.probe		= PROBE_SPI_RDID,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 16384} },
+				.block_erase = SPI_BLOCK_ERASE_21,
+			}, {
+				.eraseblocks = { {4 * 1024, 16384} },
+				.block_erase = SPI_BLOCK_ERASE_20,
+			}, {
+				.eraseblocks = { {32 * 1024, 2048} },
+				.block_erase = SPI_BLOCK_ERASE_52,
+			}, {
+				.eraseblocks = { {64 * 1024, 1024} },
+				.block_erase = SPI_BLOCK_ERASE_DC,
+			}, {
+				.eraseblocks = { {64 * 1024, 1024} },
+				.block_erase = SPI_BLOCK_ERASE_D8,
+			}, {
+				.eraseblocks = { {64 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_60,
+			}, {
+				.eraseblocks = { {64 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_C7,
+			}
+		},
+		.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD,
+		.unlock		= SPI_DISABLE_BLOCKPROTECT,
+		.write		= SPI_CHIP_WRITE256,
+		.read		= SPI_CHIP_READ,
+		.voltage	= {1650, 1950},
+	},
+
+	{
+		.vendor		= "Winbond",
 		.name		= "W25Q256JW_DTR",
 		.bustype	= BUS_SPI,
 		.manufacture_id	= WINBOND_NEX_ID,
diff --git a/include/flashchips.h b/include/flashchips.h
index 5f3bed0..3c781c7 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -1024,6 +1024,7 @@
 #define WINBOND_NEX_W25Q64_W	0x6017	/* W25Q64DW; W25Q64FV in QPI mode */
 #define WINBOND_NEX_W25Q128_W	0x6018	/* W25Q128FW; W25Q128FV in QPI mode */
 #define WINBOND_NEX_W25Q256_W	0x6019	/* W25Q256JW */
+#define WINBOND_NEX_W25R512NWEIQ	0x6020
 #define WINBOND_NEX_W25Q16JV_M	0x7015	/* W25Q16JV_M (QE=0) */
 #define WINBOND_NEX_W25Q32JV_M	0x7016	/* W25Q32JV_M (QE=0) */
 #define WINBOND_NEX_W25Q64JV	0x7017	/* W25Q64JV */

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