Here is the timeout calculation for any hardware sequencing operation:
  Worst Case Operational Delay =
        (Maximum Time consumed by a SPI operation + Any marginal
	                 adjustment)

  Timeout Recommendation for Hardware Sequencing Operation =
        ((Worst Case Operational Delay) * (#No. Of SPI Master - 1) +
                        Current Operational latency)

Assume, on Intel platform with 2 SPI master like, Host CPU and CSE, the
Timeout Calculation for SPI Write Operation would look like as below:

  Maximum Time consumed by a SPI Operation =  2 seconds
        	(for SPI Erase Operation as per Winbond Data Sheet)

  Worst Case Operational Delay = (2 seconds + 50 milliseconds) =
                                   2 seconds 50 milliseconds
  Timeout Recommendation for Hardware Seq Operation =
             (2 seconds 50 milliseconds) * (2 - 1) + 15 milliseconds
                     (for SPI Write Operation as per Winbond Data Sheet)
                        = 2 seconds 65 milliseconds